Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Register Manual
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Bits Field Name Description Type Reset
0x2: Smart idle: Idle request is acknowledged based on
the internal module activity.
0x3: Reserved
2 ENAWAKEUP Wakeup control RW 0
0x0: Wakeup is disabled.
0x1: Wakeup capability is enabled.
1 SOFTRESET Software reset. Set this bit to 1 to trigger a module reset. This RW 0
bit is automatically reset by the hardware. Read returns 0.
0x0: Normal mode
0x1: The module is reset.
0 AUTOIDLE Internal interface clock-gating strategy RW 0
0x0: Clock is running.
0x1: Automatic interface clock-gating strategy is applied
based on interface activity.
Table 19-114. Register Call Summary for Register SYSC_REG
UART/IrDA/CIR Integration
• Clocking : [0]
• Software Reset : [1]
UART/IrDA/CIR Functional Description
• Register Access Modes : [2] [3] [4] [5] [6] [7]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25]
• UART Mode Power Management : [26]
UART/IrDA/CIR Basic Programming Model
• Quick start : [27]
UART/IrDA/CIR Register Manual
• UART/IrDA/CIR Register Summary : [28] [29]
Table 19-115. SYSS_REG
Address Offset 0x058
Physical Address
See Table 19-39 to Table 19-40
Description System status register
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
RESETDONE
Bits Field Name Description Type Reset
31:1 Reserved Read returns 0. R 0x0000000
0 RESETDONE Internal reset monitoring R 0
0x0: Internal module reset is ongoing.
0x1: Reset complete
Table 19-116. Register Call Summary for Register SYSS_REG
UART/IrDA/CIR Functional Description
• Register Access Modes : [0] [1] [2]
• UART/IrDA (SIR, MIR, FIR)/CIR Mode Selection : [3] [4] [5] [6] [7] [8] [9] [10] [11]
2968UART/IrDA/CIR SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated