Texas Instruments OMAP36 Series, Technical Reference Manual

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UART/IrDA/CIR Integration
Table 19-11. UART Clocks
Clock Type Frequency Name Comments
UART1
Functional clock CORE_48M_FCLK UART1_FCLK Source and gating is the PRCM module.
Enable/disable this clock with the
PRCM.CM_FCLKEN1_CORE[13] EN_UART1 bit.
Interface clock CORE_L4_ICLK UART1_ICLK Source and gating is the PRCM module.
Enable/disable this clock with the
PRCM.CM_ICLKEN1_CORE[13] EN_UART1 bit.
Enable/disable auto-idle for this clock with the
PRCM.CM_AUTOIDLE1_CORE[13] AUTO_UART1 bit.
UART2
Functional clock CORE_48M_FCLK UART2_FCLK Source and gating is the PRCM module.
Enable/disable this clock with the
PRCM.CM_FCLKEN1_CORE[14] EN_UART2 bit.
Interface clock CORE_L4_ICLK UART2_ICLK Source and gating is the PRCM module.
Enable/disable this clock with the PRCM.
CM_ICLKEN1_CORE[14] EN_UART2 bit.
Enable/disable auto-idle for this clock with the
PRCM.CM_AUTOIDLE1_ CORE[14] AUTO_UART2
bit.
UART3
Functional clock PER_48M_FCLK UART3_FCLK Source and gating is the PRCM module.
Enable/disable this clock with the
PRCM.CM_FCLKEN_PER[11] EN_UART3 bit.
Interface clock PER_L4_ICLK UART3_ICLK Source and gating is the PRCM module.
Enable/disable this clock with the PRCM.
CM_ICLKEN_PER[11] EN_UART3 bit. Enable/disable
auto-idle for this clock with the PRCM.CM_AUTOIDLE_
PER[11] AUTO_UART3 bit.
UART4
Functional clock PER_48M_FCLK UART4_FCLK Source and gating is the PRCM module.
Enable/disable this clock with the
PRCM.CM_FCLKEN_PER[18] EN_UART4 bit.
Interface clock PER_L4_ICLK UART4_ICLK Source and gating is the PRCM module.
Enable/disable this clock with the PRCM.
CM_ICLKEN_PER[18] EN_UART4 bit. Enable/disable
auto-idle for this clock with the PRCM.CM_AUTOIDLE_
PER[18] AUTO_UART4 bit.
The idle and wake-up processes use a handshake protocol between the PRCM module and the UARTs
(for a description of the protocol, see
Chapter 3 , Power, Reset, and Clock Management). The
UARTi. SYSC_REG [4:3] IDLEMODE field controls the UART idle mode.
19.3.1.2 Hardware Reset
Table 19-12 lists the UART reset domain.
Table 19-12. Reset Domain
Peripherals Reset Domain
UART1 CORE_RST
UART2 CORE_RST
UART3 PER_RST
UART4 PER_RST
2887 SWPU177N – December 2009 – Revised November 2010 UART/IrDA/CIR
Copyright © 2009–2010, Texas Instruments Incorporated