Public Version
Display Subsystem Basic Programming Model
www.ti.com
The pixels are formatted based on the specified cycle format. If two pixels are written into the 32-data
register, the DSS.
[8:7] L4FORMAT bit field indicates the number of pixels for each L4
access to the register and the order of the pixels
If the previous data are not processed, the DSS.
[8] BUSY bit is set by hardware
and any access for writing new data is stalled. When the DSS.
[8] BUSY bit is reset
by hardware, the access is not stalled.
•
Read/status register
Send through the command and parameter registers the correct information to receive data in the data
or status register. The read data from the LCD panel is initiated by writing into the DSS.
or
DSS.
registers. In this case, the DSS.
[8] BUSY bit is set until the
data are available in the register.
When the DSS.
[8] BUSY bit is set by hardware, the read or write access is stalled
until the register is updated with a new value from the LCD panel. To avoid the stall, the software can
poll the DSS.
[8] BUSY bit until it is reset by hardware. To receive the data, send
the appropriate command/parameters.
7.5.7.3.9 RFBI Configuration Flow Charts
The RFBI configuration depends on the trigger mode used by the application. The available trigger modes
are:
•
Internal trigger mode when setting the DSS.
[3:2] TRIGGERMODE bit field to 0x0
•
External trigger mode:
–
TE external trigger mode when setting the DSS.
[3:2] TRIGGERMODE bit field to
0x1
–
HSYNC/VSYNC external trigger mode when setting the DSS.
[3:2] TRIGGERMODE
bit field to 0x2
gives an example of how to program and use the RFBI module:
1770
Display Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
