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SDRAM Controller (SDRC) Subsystem
discusses the SDRAM device features to consider.
discusses the
SDRC controller features to consider. As an example,
lists chosen SDRAM parameters
versus the supported characteristics of the SDRC controller.
10.2.6.4.1 SDRAM Device Parameters
Several settings must be considered when selecting an SDRAM device to interface with the SDRC
controller:
•
SDRAM type
•
Operating voltage
•
Maximum operating frequency
•
Maximum memory size
•
Memory organization:
–
Number of banks
–
Data bus width
•
Burst length
•
Page size
•
Column address strobe (CAS) latency
•
Refresh rate
•
AC timing parameters and especially the access time parameter tAC
These parameters are defined in the SDRAM device datasheet and must meet the SDRC controller
specifications.
10.2.6.4.2 SDRC Controller Characteristics
Keeping the SDRAM device settings in mind, the SDRC controller supports:
•
Supported device type: Up to two mobile single data rate (M-SDR) SDRAMs, or up to two low-power
double data rate (LPDDR) SDRAMs.
•
Operating voltage: VDD = VDDQ = 1.7 V to 1.9 V; VSS = VSSQ = 0.0 V (and LVCMOS 1.8 V I/Os)
•
Temperature range: –25°C to 85°C ambient
•
Maximum supported operating Frequency: 200 MHz (condition: single device optimized board layout).
•
Maximum supported memory size: 128M bytes per external SDRAM bank (256M- and 512M-byte
SDRAM may be supported, depending on their implementation)
•
Minimum supported memory size: 2M bytes
•
Maximum SDRC addressing capability: 1G byte
•
Memory organization:
–
Number of internal SDRAM banks: two (for 2 and 4 MB memory device only) or four banks (other
memory device only)
–
Data path to external SDRAM memory: 16- or 32-bit
•
Burst Length: Burst of 2 (M-SDR) and burst of 4 (LPDDR)
•
Page size: Programmable value (up to 16K bytes)
•
Column address strobe latency (CL): 1 to 5 system clock cycles
•
Refresh intervals: Programmable value
•
Major operation is 3-3-3 (CL-tRCD-tRP) conditions.
–
CL = 3
–
tRCD = 3 clocks cycle time
–
tRP = 3 clocks cycle time
–
tRRD = 2 clocks cycle time
–
tRAS = 7 clocks cycle time
–
tRC = 10 clocks cycle time
2299
SWPU177N – December 2009 – Revised November 2010
Memory Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
