Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Table 5-770. iLF_CPUSTATUSREG
Address Offset 0x0000 05F0
Physical Address 0x000A 15F0 Instance iLF
Description CPU Status Register provides information about the progress of the CPU execution
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PC CYCLECOUNT
RESERVED
EXECSTATE
OPCODEERROR ENDPGMERROR
WRITEREGERROR
DETECTEDSTOPSEQ
DETECTEDENDOFPGM
Bits Field Name Description Type Reset
31 RESERVED Read returns 0. R 0x0
30 DETECTEDENDOFPGM This bit is set to '1' when, in Debug mode, an EndPgm() R 0x0
instruction or the last instruction of the program buffer
has been reached and it is not a LoadInstBuf()
instruction.
This bit is cleared by a StartSeq() command when in
INITIALIZED or COMPLETED state.
29 DETECTEDSTOPSEQ This bit is set to '1' when a StopSeq() has been issued R 0x0
and the iME is in Halted state. Execution of StopSeq() is
postponed to the time when the CPU gets out of the
Halted state.
This bit is cleared when the StopSeq() command is
effectively executed.
28 ENDPGMERROR This bit is set to '1' when the last instruction of the R 0x0
program buffer is reached and no EndPgm() or
LoadInstBuf() instruction have been detected in the
program buffer.
This bit is cleared by a StartSeq() command when in
INITIALIZED or COMPLETED state.
27 OPCODEERROR This bit is set to '1' when an unknown opcode is decoded R 0x0
from the main program. The following instruction of the
sequence is then executed.
This bit is cleared by a StartSeq() command when in
INITIALIZED or COMPLETED state.
26 WRITEREGERROR This bit is set to '1' when attempting to write an internal R 0x0
register through an OCP write, while in EXECUTING
state.
This bit is cleared by a StartSeq() command when in
INITIALIZED or COMPLETED state.
25:24 EXECSTATE Execution States: R 0x0
00 = Initialized,
10 = Executing,
01 = Halted,
11 = Completed.
23:16 PC Number of instruction currently executing. R 0x00
Bit #7 is always 0 (PC values range from 0x00 to 0x7f)
15:0 CYCLECOUNT Total number of cycles executed. R 0x0000
Table 5-771. Register Call Summary for Register iLF_CPUSTATUSREG
IVA2.2 Subsystem Register Manual
• iLF Register Mapping Summary : [0]
1073 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated