VIDFIRVINC[11:0] = 1024 x
VIDORGSIZEY[10:0]
VIDSIZEY[10:0]
dss-E118
VIDFIRHINC[11:0] = 1024 x
VIDORGSIZEX[10:0]
VIDSIZEX[10:0]
dss-E119
Public Version
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Display Subsystem Use Cases and Tips
•
When the VIDRESIZEENABLE[1] bit is set to 1, the video vertical up/downsampling block is enabled.
When set to 0, the vertical resize processing is disabled.
•
When the VIDRESIZEENABLE[0] bit is set to 1, the video horizontal up/downsampling block is
enabled. When set to 0, the horizontal resize processing is disabled.
•
When the VIDRESIZEENABLE[1:0] is set to 0x3, both horizontal and vertical resize processing are
enabled.
NOTE:
•
Set a valid configuration before enabling the video up/downsampling block.
•
Vertical and horizontal downsampling are limited to a 0.25 resize factor. When
processing a down-scaling with a vertical factor between 0.5 and 0.25, a 5-tap filter
configuration must be used. See
for more information concerning the
filter coefficients.
7.6.1.3.3 Factor
The following register bit fields define the increment value of the video up/downsampling block for video
pipeline n:
•
Vertical up/downsampling increment value (DSS.
[27:16] VIDFIRVINC bit field, with n
= 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using the
following equation:
(17)
NOTE:
•
If the VIDFIRVINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If
VIDSIZEY[10:0] equals 0x1, VIDSIZEY[10:0] is replaced by 0x2 in the previous
equation.
•
The VIDORGSIZEY[10:0] and VIDSIZEY[10:0] bit field values must be programmed with
the value desired minus 1.
•
Horizontal up/downsampling increment value (the DSS.
[11:0] VIDFIRHINC bit field,
with n = 1 or 2): The unsigned integer value range is [1:4096]. The software calculates the value using
the following equation:
(18)
NOTE:
•
If the VIDFIRHINC[11:0] bit field value is greater than 4096, it is clipped to 4096. If
VIDSIZEX[10:0] equals 1, VIDSIZEX[10:0] is replaced by 2 in the previous equation.
•
The VIDORGSIZEX[10:0] and VIDSIZEX[10:0] bit field values must be programmed with
the value desired minus 1.
7.6.1.3.4 Initial Phase
•
Vertical up/downsampling accumulator value DSS.
[25:16] VIDVERTICALACCU
bit fields
The unsigned integer value range is [0:1023]. The accumulator value indicates on which phase the
vertical filtering starts. The value 0 indicates that the phase 0 is the first phase used by the hardware to
generate the first data.
•
Vertical up/downsampling accumulator value DSS.
[9:0] VIDHORIZONTALACCU
bit fields
1783
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
