Texas Instruments OMAP36 Series, Technical Reference Manual

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Start
End
Use
translation
tables?
Write
translation
tables
Time-
critical
entries?
Write
TLB entries
Write
TLB entries
Lock TLB
entries
Lock TLB
entries
Disable
walking logic
Enable
walking logic
Enable
MMU
Y
Y
N
N
MMU-018
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MMU Basic Programming Model
Figure 15-18. MMU Configuration Strategies
MMU components must be set up before the MMU can be used for address translation. The following
steps are required:
• Initialize translation tables and the table walker logic if translation tables are used.
• Write TLB entries if required.
• Enable MMU.
Next paragraph explains how to configure the IVA2.2 MMU by directly writing the entries in the Translation
Look-aside Buffer (TLB). The focus of this example is to explain the required configuration steps rather
than to provide the most efficient implementation.
15.4.1 Writing TLB Entries Statically
This example deals with predefined translation strategy, that is, entries are “statically” written in the TLB.
This method avoids the need to write Translation tables in memory and is commonly used for relatively
small address spaces. It ensures that the translation of time-critical data accesses execute as fast as
possible with entries already present in the TLB. These entries must be locked to prevent them from being
overwritten. To setup the MMU follow those steps:
1. Reset MMU: write MMU_SYSCONFIG [1] SOFTRESET = 1 and wait for the system reset completion
by polling MMU_SYSSTATUS [0] RESETDONE until it is equal to 1.
2. Set MMU_SYSCONFIG [0] AUTOIDLE bit to enable power saving via automatic interface clock gating.
After reset the Table walking logic remain disabled ( MMU_CNTL [2] TWLENABLE = 0), the TLB is
empty and the victim pointer points to the first TLB entry, Entry 0 ( MMU_LOCK [8:4] CURRENTVICTIM
at 0).
To initialize a TLB entry, follow those steps:
3. Load the Virtual Address (VATAG), the preserved (P=1) and valid (V=1) bits and the page size (small
or large page, section, supersection) into MMU_CAM register.
2681 SWPU177N – December 2009 – Revised November 2010 Memory Management Units
Copyright © 2009–2010, Texas Instruments Incorporated