Texas Instruments OMAP36 Series, Technical Reference Manual

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MMU Register Manual
Bits Field Name Description Type Reset
Read 0x1: Never happens
Write 0x1: Load TLB data
Table 15-31. Register Call Summary for Register MMU_LD_TLB
Basic Programming Model
• Writing TLB entries statically : [0]
MMU Register Manual
• Register Mapping Summary : [1]
Table 15-32. MMU_CAM
Address Offset 0x058
Physical address 0x480B D458 Instance MMU1 (Camera ISP MMU)
0x5D00 0058 MMU2 (IVA2.2 MMU)
Description This register holds a CAM entry.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VATAG Reserved P V
PAGESIZE
Bits Field Name Description Type Reset
31:12 VATAG Virtual address tag RW 0x00000
11:4 Reserved Reads return 0. Write 0s for future compatibility. R 0x00
3 P Preserved bit RW 0
0x0: TLB entry can be flushed
0x1: TLB entry is protected against flush
2 V Valid bit RW 0
0x0: TLB entry is invalid
0x1: TLB entry is valid
1:0 PAGESIZE Page size RW 0x0
0x0: Section (1MB)
0x1: Large page (64KB)
0x2: Small page (4KB)
0x3: Supersection (16MB)
Table 15-33. Register Call Summary for Register MMU_CAM
MMU Functional Description
• TLB Entry Format : [0]
Basic Programming Model
• Writing TLB entries statically : [1]
• Deleting TLB Entries : [2]
MMU Register Manual
• Register Mapping Summary : [3]
• MMU Register Description : [4]
2695 SWPU177N – December 2009 – Revised November 2010 Memory Management Units
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