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MMU Register Manual
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
GLOBALFLUSH
Bits
Field Name
Description
Type
Reset
31:1
Reserved
Reads return 0. Write 0s for future compatibility.
RW
0x00000000
0
GLOBALFLUSH
Flush all the non-protected TLB entries when set
RW
0
Read 0x0:
Always returns 0
Write 0x0:
No functional effect
Read 0x1:
Never happens
Write 0x1:
Flush all the non-protected TLB entries
Table 15-37. Register Call Summary for Register MMU_GFLUSH
MMU Functional Description
•
Basic Programming Model
•
:
MMU Register Manual
•
Table 15-38. MMU_FLUSH_ENTRY
Address Offset
0x064
Physical address
0x480B D464
Instance
MMU1 (Camera ISP MMU)
0x5D00 0064
MMU2 (IVA2.2 MMU)
Description
This register flushes the entry pointed to by the CAM virtual address.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
FLUSHENTRY
Bits
Field Name
Description
Type
Reset
31:1
Reserved
Reads return 0. Write 0s for future compatibility.
RW
0x00000000
0
FLUSHENTRY
Flush the TLB entry pointed by the virtual address (VATag) in
RW
0
register, even if this entry is set protected
Read 0x0:
Always returns 0
Write 0x0:
No functional effect
Read 0x1:
Never happens
Write 0x1:
Flush all the TLB entries specified by the CAM register
Table 15-39. Register Call Summary for Register MMU_FLUSH_ENTRY
Basic Programming Model
•
:
MMU Register Manual
•
2697
SWPU177N – December 2009 – Revised November 2010
Memory Management Units
Copyright © 2009–2010, Texas Instruments Incorporated
