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MMU Basic Programming Model
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4. Load the Physical Address (PHYSICALADDRESS), the endianness (ENDIANNESS = 0), element size
(ELEMENTSIZE) and mixed page attributes bits (MIXED) into
register.
5. Specify the TLB entry you want to write by setting the
[8:4] CURRENTVICTIM pointer.
Start with TLB Entry 0 and increment this pointer for each subsequent entry you want to write.
6. Load the specified entry in the TLB by setting
[0] LDTLBITEM = 1.
7. Repeat steps 3 to 6 for all entries you want to write.
Remember to increment the
[8:4] CURRENTVICTIM pointer with each entry you are
writing. To prevent replacement of TLB entries see
, Protecting TLB Entries.
To enable error handling when more than one valid entry exists in the TLB for the given virtual address
or when no translation is found for the virtual address required (with the Table walking logic disabled):
8. Enable Multi-hit fault and TLB miss with table walker disabled interrupts by writing 1 in
[4] MULTIHITFAULT and
[0] TLBMISS.
9. To determine the cause of the fault interrupt the interrupt service routine (ISR) can read corresponding
bits. The virtual address that caused the fault can be determined by reading
.
NOTE:
MMU errors result in a memory stall; the MMU will not process any request until the cause
of the error has been addressed.
To enable memory translations enable MMU (virtual addresses are treated as physical addresses
when MMU is disabled):
10. Set
[1] MMUENABLE = 1 to enable memory translations enable the MMU (virtual
addresses are treated as physical addresses when the MMU is disabled.
15.4.1.1 Protecting TLB Entries
The first n TLB entries (with n < total number of TLB entries) can be protected from being overwritten with
new translations. This is useful to ensure that certain commonly used or time-critical translations are
always in the TLB and do not require retrieval via the table walking process.
The entry protection mechanism is shown in
. To protect the first n TLB entries, set the
[12:10] BASEVALUE bit field for the camera MMU (MMU2.
[14:10]
BASEVALUE field for the IVA2.2 MMU) to n.
15.4.1.2 Deleting TLB Entries
Two mechanisms exist to delete TLB entries. All unpreserved TLB entries, i.e., TLB entries that were
written with the preserved bit set to zero, can be deleted by invoking a TLB flush. Such a TLB flush is
invoked by setting the MMUn.
[0] GLOBALFLUSH bit.
Individual TLB entries can be flushed, regardless of the preserved bit setting, by specifying its virtual
address in the MMUn.
register and setting the MMUn.
[0] FLUSHENTRY
bit.
The preserved bit should only be used on protected TLB entries, as it does not prevent replacement by
the table walking logic.
15.4.1.3 Reading TLB Entries
TLB entries can be read by you to determine the TLB content at runtime. In doing so, the TLB entry
number is specified by setting the MMUn.
[8:4] CURRENTVICTIM pointer. CAM and RAM
parts of the TLB entry can then be read in the MMUn.
and MMUn.
registers, respectively.
15.4.2 Programming the MMU Dynamically
When translation tables are used for MMU address translation they must be properly set up and the table
walking logic must be enabled.
The following page sizes are supported:
2682
Memory Management Units
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
