Texas Instruments OMAP36 Series, Technical Reference Manual

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MMU Register Manual
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Table 15-28. MMU_LOCK
Address Offset 0x050
Physical address 0x480B D450 Instance MMU1 (Camera ISP MMU)
0x5D00 0050 MMU2 (IVA2.2 MMU)
Description This register locks some of the TLB entries or specifies the TLB entry to be read.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved BASEVALUE CURRENTVICTIM Reserved
Reserved
Bits Field Name Description Type Reset
31:15 Reserved Reads return 0. Write 0s for future compatibility. R 0x00000
14:10 BASEVALUE Locked entries base value RW 0x00
Note: In the Camera MMU instance, BASEVALUE is a 3-bit field, ie.
bits 13 and 14 are reserved.
9 Reserved Reads return 0. Write 0s for future compatibility. R 0
8:4 CURRENTVICTIM Current entry to be updated either by the TWL or by the software or RW 0x00
TLB entry to be read
Note: In the Camera MMU instance, CURRENTVICTIM is a 3-bit field,
ie. bits 7 and 8 are reserved.
Write value: TLB entry to be updated by software or TLB entry to be
read
Read value: TLB entry to be updated by table walk logic
3:0 Reserved Reads return 0. Write 0s for future compatibility. R 0x0
Table 15-29. Register Call Summary for Register MMU_LOCK
Basic Programming Model
• Writing TLB entries statically : [0] [1] [2]
• Protecting TLB Entries : [3] [4]
• Reading TLB Entries : [5]
MMU Register Manual
• Register Mapping Summary : [6] [7]
Table 15-30. MMU_LD_TLB
Address Offset 0x054
Physical address 0x480B D454 Instance MMU1 (Camera ISP MMU)
0x5D00 0054 MMU2 (IVA2.2 MMU)
Description This register loads a TLB entry (CAM+RAM).
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
LDTLBITEM
Bits Field Name Description Type Reset
31:1 Reserved Reads return 0. Write 0s for future compatibility R 0x00000000
0 LDTLBITEM Write (load) data in the TLB RW 0
Read 0x0: Always returns 0
Write 0x0: No functional effect
2694 Memory Management Units SWPU177N – December 2009 – Revised November 2010
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