Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 2689 / 3738

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MMU Register Manual
Bits Field Name Description Type Reset
1 SOFTRESET Software reset. This bit is automatically reset by the hardware. During reads, it RW 0
always returns 0.
Read 0x0: Always returns 0
Write 0x0: No functional effect
Read 0x1: Never happens
Write 0x1: The module is reset.
0 AUTOIDLE Internal interconnect clock gating strategy RW 0
0x0: Interconnect clock is free-running.
0x1: Automatic interconnect clock gating strategy is applied, based on
the interconnect interface activity.
Table 15-13. Register Call Summary for Register MMU_SYSCONFIG
MMU Integration
• System Power Management : [0] [1] [2]
• Module Power Saving : [3] [4]
• Reset : [5]
Basic Programming Model
• Writing TLB entries statically : [6] [7]
MMU Register Manual
• Register Mapping Summary : [8]
Table 15-14. MMU_SYSSTATUS
Address Offset 0x014
Physical address 0x480B D414 Instance MMU1 (Camera ISP MMU)
0x5D00 0014 MMU2 (IVA2.2 MMU)
Description This register provides status information about the module, excluding the interrupt status information.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved Reserved
RESETDONE
Bits Field Name Description Type Reset
31:8 Reserved Reads return 0. R 0x000000
7:1 Reserved Reads return 0. R 0x00
Reserved for interconnect-socket status information
0 RESETDONE Internal reset monitoring R -
0x0: Internal module reset in ongoing.
0x1: Reset completed
Table 15-15. Register Call Summary for Register MMU_SYSSTATUS
MMU Integration
• Reset : [0]
Basic Programming Model
• Writing TLB entries statically : [1]
MMU Register Manual
• Register Mapping Summary : [2]
2689 SWPU177N – December 2009 – Revised November 2010 Memory Management Units
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