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Display Subsystem Integration
•
Graphics pipe is enabled and data fetch is not completed for graphics window, and the number of data
bytes in FIFO is less than the low threshold programmed value.
•
Video1 pipe is enabled and data fetch is not completed for video1 window, and the number of data
bytes in FIFO is less than the low threshold programmed value.
•
Video2 pipe is enabled and data fetch is not completed for video2 window, and the number of data
bytes in FIFO is less than the low threshold programmed value.
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The current pixel is the last pixel displayed on the LCD panel if it is not the last frame.
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The current pixel is the last pixel displayed on the digital panel if it is not the last frame.
If software users set the DSS.
[17] FIFOFILLING bit, when one of the active pipe
reaches the low threshold and should refill the FIFO for the current frame, the other pipes also refill
their own FIFOs, even if the low threshold has not been reached. This is used to improve the
probability of increasing the time when there is no access to the L3 interconnect (MStandby asserted,
affects power savings).
Once the wake-up signal is asserted, the WAKEUP interrupt request is generated. The wake-up signal
is deasserted when the idle request is no longer activated.
7.3.1.4.5 Standby Mode
As part of the system-wide power-management scheme, the display controller can enter standby mode.
To configure the display controller, write the DSS.
[13:12] MIDLEMODE bit field (00:
Forced standby; 01: No standby; 10: Smart standby) in one of the following standby modes:
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Forced standby mode (default mode): The module enters standby mode when the module is disabled.
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No standby mode: The module never enters standby mode.
•
Smart standby mode: The module enters standby state when the DISPC module is disabled or when
all the three following events occur:
–
Graphics pipe is disabled or graphics pipe is enabled but data fetch completed for graphics window,
or graphics pipe is enabled and data fetch is not completed and number of data bytes in FIFO is
greater than the high threshold programmed value.
–
Video1 pipe is disabled or video1 pipe is enabled but data fetch completed for video1 window, or
video1 pipe is enabled and data fetch is not completed and number of data bytes in FIFO is greater
than the high threshold programmed value.
–
Video2 pipe is disabled or video2 pipe is enabled but data fetch completed for video2 window, or
video2 pipe is enabled and data fetch is not completed and number of data bytes in FIFO is greater
than the high threshold programmed value.
When in standby mode, the display controller does not generate transactions on the L3 master port.
Standby is active when the PRCM module confirms this mode.
The display subsystem standby mode activity can be monitored with the PRCM.CM_IDLEST_DSS[0]
ST_DSS status register. When this register is read to 0, the display subsystem is accessible and the
interface clock running; when it is read to 1, the display subsystem is in standby mode.
7.3.1.4.5.1 Conditions to Exit Standby Mode
The following conditions allow the subsystem to exit standby mode:
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Forced standby mode: Standby mode is exited when the display controller is enabled.
•
Smart standby mode: Standby mode is exited when any one of the following events occurs:
–
Graphics pipe is enabled and data fetch is not completed for graphics window, and number of data
bytes in FIFO is less than the low threshold programmed value.
–
Video1 pipe is enabled and data fetch is not completed for video1 window, and number of data
bytes in FIFO is less than the low threshold programmed value.
–
Video2 pipe is enabled and data fetch is not completed for video2 window, and number of data
bytes in FIFO is less than the low threshold programmed value.
1625
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated
