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SDRAM Controller (SDRC) Subsystem
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When fixed delay mode is enabled, a counter (programmable through the
[23:16]MODEFIXEDDELAYINITLAT field) based on the input frequency allows the SDRC to stall all
incoming requests. Once this counter expires, the SDRC starts accessing the memory. The DLL
characterization shows that this feature is not useful and that this value shall be set to 0x0, leading
actually to a null delay.
The DLL can be put in idle mode using the
[4] DLLIDLE bit. When in idle mode, the
DLL lock is lost. The precharge voltage is kept stable to enable faster relock when going back to a
functional state. If set, this bit overrides the ENADLL bit. Thus, avoid completely powering down the DLL
by keeping the precharge voltage and cutting off the analog loop. Exiting from this idle mode saves some
clock cycles compared to exiting from power-down mode. Refer to the note (DLL behavior upon a warm
reset assertion) in
, Dynamic Low-Power Operating Modes). Furthermore, the
[6:5] DLLMODEONIDLEREQ field defines the modes (power-down/DLLIDLE/No
action) of the DLL that are automatically entered upon an Idle_req assertion. The DLL mode
(TrackedDelay or ModeFixedDelay mode) is updated only when Idle_req/Idle_ack handshake protocol
occurs, warm reset occurs, PWRDN is enabled, or DLLIDLE mode enabled.
Power-down mode is asserted upon warm reset assertion. If power-down and DLLIDLE are asserted
simultaneously, power-down overwrites DLLIDLE mode inside the DLLCDL cell.
To modify the SDRC input clock when the DLL is locked and active, the DLL must first enter either its idle
mode or its power-down mode. The SDRC input frequency can be changed by using any of the following
scenarios:
•
Internal signals handshaking protocol with PRCM module
•
Warm reset event
•
DLLIDLE mode
•
Power-down mode
The ENADLL bit controls the PWRDN mode of the DLL module.
The LOCKDLL bit sets the DLL in TrackedDelay (lock) or ModeFixedDelay (unlock) mode.
ModeFixedDelay mode is supported up to 83 MHz.
See
for more information on the CDL/DLL module.
DLLMODEONIDLEREQ is of no importance to the Idle_ack generation. In case DLLMODEONIDLEREQ =
2 and Idle_req occurs, Idle_ack can be generated and SDRC/core can go to idle; however, recovery from
this state may be incorrectly performed and the DLL cannot relock. If this happens, the only solution to
recover is to disable and then re-enable the DLL. DLLMODEONIDLEREQ = 2 is not a valid configuration
under Idle_req assertion and must not be used. DLLMODEONIDLEREQ can be set 0 or 1, depending on
whether the priority is shorter wake-up latency or lower power consumption.
10.2.5.3.5 Mode Register Programming and Modes of Operation
The SDRC contains a group of registers known as the memory mode registers. These registers define the
operational modes of the target SDRAM.
•
MR: Mode register used to define operational parameters common to SDR and DDR SDRAMs.
•
EMR1: Extended mode used to define operational parameters exclusive to DDR SDRAM (irrelevant to
the SDRC since regular DDRs are not supported).
•
EMR2: Extended mode used to define operational parameters exclusive to mobile SDRAM.
10.2.5.3.5.1 Mode Register (MR)
The 12-bit SDRC.
register (p = 0 or 1 for CS0 or CS1) is common to all SDR and DDR
SDRAMs and controls the following parameters:
•
Write burst mode
•
CAS latency
•
Serial/interleaved mode
•
Burst length
When programming the SDRC.
bit fields (where p = 0 or 1 for SDRC CS0 or CS1), consider
the following:
2270
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
