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General-Purpose Timers
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Any 16-bit write access must be least-significant bit (LSB) first, and the second write access must be
most-significant bit (MSB). Write operations to the GP timer registers (GPTi.
, GPTi.
, GPTi.
) can skip the MSB access if it is not necessary to
update the 16 MSBs of the register.
Write operations to any functional register (GPTi.
, GPTi.
, GPTi.
, and
, GPTi.
, GPTi.
, GPTi.
, and GPTi.
for GPTIMER1,
GPTIMER2, and GPTIMER10) must be complete (the MSB must be written even if the MSB data is not
used).
16.2.6.1 Writing to Timer Registers
The host uses the L4 interface to write the following registers synchronously with the timer interface clock:
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
GPTIMER1, GPTIMER2, and GPTIMER10 also have the following registers:
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
•
GPTi.
In 16-bit access mode, the 16 LSBs must be written before writing to the 16 MSBs.
16.2.6.1.1 Write Posting Synchronization Mode
This mode is used if the GPTi.
[2] POSTED bit is set to 1.
This mode uses a posted write scheme to update any internal register (GPTi.
, GPTi.
, GPTi.
, GPTi.
, GPTi.
, GPTi.
, and
for GPTIMER1, GPTIMER2, and GPTIMER10). Therefore, the write transaction is
immediately acknowledged on the L4 interface, although the effective write operation occurs later,
because of a resynchronization in the timer clock domain. The advantage is that neither the interconnect
nor the device that requested the write transaction is stalled.
For each register, a status bit is provided in the timer write-posted status register GPTi.
. In this
mode, it is mandatory that the software checks this status bit prior to any write access. In case a write is
attempted to a register with a previous access pending, the previous access is discarded without notice.
The timer module updates the timer counter register value synchronously with the L4 clock. Consequently,
any read access to the timer counter register GPTi.
does not add any resynchronization latency; the
current value is always available.
If a write access is pending for a register, reading from this register does not yield a correct result.
Software synchronization must be used to avoid incorrect results.
The drawback of this automatic update mechanism is that it assumes a given relationship between the
timer interface frequency and the timer clock frequency.
Functional frequency range: freq(timer clock) < freq(L4 interface clock)/4
2722
Timers
SWPU177N – December 2009 – Revised November 2010
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