Public Version
General-Purpose Timers Register Manual
www.ti.com
Bits
Field Name
Description
Type
Reset
[7:4] Major revision
[3:0] Minor revision
Examples: 0x10 for 1.0, 0x21 for 2.1
Table 16-17. Register Call Summary for Register TIDR
General-Purpose Timers
•
General-Purpose Timers Register Manual
•
GP Timer Register Mapping Summary
Table 16-18. TIOCP_CFG
Address Offset
0x010
Physical Address
0x4831 8010
Instance
GPT1
0x4903 2010
GPT2
0x4903 4010
GPT3
0x4903 6010
GPT4
0x4903 8010
GPT5
0x4903 A010
GPT6
0x4903 C010
GPT7
0x4903 E010
GPT8
0x4904 0010
GPT9
0x4808 6010
GPT10
0x4808 8010
GPT11
Description
This register controls the various parameters of the GP timer L4 interface.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
Reserved
Reserved
EMUFREE
AUTOIDLE
IDLEMODE
SOFTRESET
ENAWAKEUP
CLOCKACTIVITY
Bits
Field Name
DESCRIPTION
Type
Reset
31:10
Reserved
Write 0s for future compatibility. Reads return 0.
R
0x0000000
9:8
CLOCKACTIVITY
Clock activity during wakeup mode period:
RW
0x0
0x0:
L4 interface and Functional clocks can be
switched off.
0x1:
L4 interface clock is maintained during wake-up
period; Functional clock can be switched off.
0x2:
L4 interface clock can be switched off; Functional
clock is maintained during wake-up period.
0x3:
L4 interface and Functional clocks are maintained
during wake-up period.
7:6
Reserved
Write 0s for future compatibility. Reads return 0.
R
0x0
5
EMUFREE
Emulation mode
RW
0
0x0:
Timer counter frozen in emulation
0x1:
Timer counter free-running in emulation
4:3
IDLEMODE
Power management, req/ack control
RW
0x0
2728
Timers
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated