Texas Instruments OMAP36 Series, Technical Reference Manual

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SDRAM Controller (SDRC) Subsystem
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Bits Field Name Description Type Reset
2 DDRTYPE DDR memory type (assuming RAMTYPE = 01) RW 0x-
0x0: Mobile DDR
0x1: Reserved for future use
1:0 RAMTYPE Memory type RW 0x-
0x0: SDR-SDRAM (single data rate)
0x1: DDR-SDRAM (double data rate)
0x2: Reserved
0x3: Reserved
Table 10-175. SDRC_MR_p
Address Offset 0x0000 0084 + (0x0000 0030 * p) Index p = 0 to 1
Physical Address 0x6D00 0084 + (0x0000 0030 * p) Instance SDRC
Description This 12-bit register corresponds to the JEDEC SDRAM MR register, with the standard bit fields. All 12 bits are
loaded into memory for future extension support. The SDRC keeps an internal copy register used internally; that
is, returned when a read access is performed at that address. Load into memory on interconnect write access
using MRS command with BA1,BA0 = 0,0.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED CASL BL
SIL
WBST
ZERO_1 ZERO_0
Bits Field Name Description Type Reset
31:12 RESERVED Write 0s for future compatibility. Read returns 0s. RW 0x00000
11:10 ZERO_1 Write 0s, as required by memory specifications. Read returns 0. RW 0x0
9 WBST Write burst support must be zero. RW 0x0
0x0: Write burst equals read burst
0x1: Write burst disable (single write access only)
8:7 ZERO_0 Write 0s, as required by memory specifications. Read returns 0s. RW 0x0
6:4 CASL CAS latency as defined by clock periods RW 0x2
0x1: CAS latency = 1
0x2: CAS latency = 2
0x3: CAS latency = 3
0x4: CAS latency = 4
0x5: CAS latency = 5
3 SIL Serial or interleaved mode: must be zero RW 0x0
0x0: Serial mode (always used)
0x1: interleaved mode (never used)
2:0 BL Memory burst length RW 0x4
0x0: Burst length = 1 - Not supported
0x1: Burst length = 2 - SDR memory only
0x2: Burst length = 4 - DDR memory only
0x3: Burst length = 8 - Not supported
0x4: Reserved
0x5: Reserved
0x6: Reserved
0x7: Full page - Not supported
2326 Memory Subsystem SWPU177N – December 2009 – Revised November 2010
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