HS
CCP2_LCM_SRC_OFST
CCP2_LCM_SRC_ADDR
CCP2_LCM_VSIZE
CCP2_LCM_HSIZE[11:0]
SKIP
CCP2_LCM_HSIZE[27:16]
COUNT
camisp-205
VS
Public Version
Camera ISP Functional Description
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6.4.2.2.5.1 Camera ISP CSI1/CCP2B Read Data From Memory
shows the data organization in memory.
Figure 6-63. Camera ISP CSI1/CCP2B Data Organization in Memory
The user chooses the start address and the line length using the
and
registers. The image start address normally must point to the beginning of a line
because of packing constraints. However it does not necessarily point to the first line of the frame in
memory. The
[27:16] COUNT bit field specifies the total line count to be read from
memory.
It is also possible to skip a certain pixel count (
[11:0] SKIP) from the start of the line.
However, they are not sent to the video port or back to memory. The
[27:16] COUNT
bit field specifies the horizontal size of the image. The pixels after the right boundary of the image are not
read from memory.
When data are sent to the video port, throughput is imposed by the selected video port clock. Otherwise, it
is imposed by the selected interconnect read port clock. The interconnect read rate can be throttled
(limiting the maximum data read speed for memory-to-memory operation) using the
[4:3] READ_THROTTLE bit field. Therefore, it is possible to read the unused data at a higher rate than the
used video port data rate. This provides better performance than framing the image in the Video
processing hardware.
The data storage format in memory is defined by the
[18:16] SRC_FORMAT, and
[23] SRC_PACK registers.
Not all IO format combinations are valid. See
and
for more information.
shows how data are packed in memory. Pixel order (left to right in the image) is alphabetical
(a,b,c). Therefore, data storage is little endian.
1170
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated