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Camera ISP Register Manual
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Table 6-191. Register Call Summary for Register CCP2_LCx_DAT_PONG_ADDR (continued)
Camera ISP Register Manual
•
Camera ISP CCP2 Register Summary
•
Camera ISP CCP2 Register Description
Table 6-192. CCP2_LCx_DAT_OFST
Address Offset
0x0000 0078 + (x * 0x30)
Index
x = 0 to 3
Physical Address
0x480B C478 + (x * 0x30)
Instance
ISP_CCP2
Description
DATA MEMORY ADDRESS OFFSET REGISTER - LOGICAL CHANNEL x. This register sets the offset,
which is applied on the destination address after each line is written to memory. This register applies for
both
and
. For example, it enables 2D
data transfers of the pixel data into a frame buffer. In such case, the pixel data and frame buffer data
have the same data format. Note that the 5 LSBs are ignored: the offset shall be a multiple of 32 bytes.
The use of this register is limited to the following data formats: YUV422 little-endian, YUV422
big-endian, RGB565, EXP16, EXP32. This register is shadowed; modifications
are taken into account after the next FSC synchronization code.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
OFST
RESERVED
Bits
Field Name
Description
Type
Reset
31:5
OFST
Line offset programmed in bytes
RW
0x0000000
If OFST = 0, the data are written contiguously in memory.
Otherwise, OFST sets the destination offset between the
first pixel of the previous line and the first pixel of the
current line.
(1)
4:0
RESERVED
Write 0s for future compatibility. Read returns 0.
RW
0x00
(1)
An Interconnect access (read/write) is required to properly update the CCP2_LCx_DAT_OFST register.
Table 6-193. Register Call Summary for Register CCP2_LCx_DAT_OFST
Camera ISP Basic Programming Model
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Camera ISP CSI1/CCP2B Register Accessibility During Frame Processing
:
•
Camera ISP CSI1/CCP2B Pixel Data Region
[1] [2] [3] [4] [5] [6] [7] [8] [9] [10]
Camera ISP Register Manual
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Camera ISP CCP2 Register Summary
Table 6-194. CCP2_LCM_CTRL
Address Offset
0x0000 01D0
Physical Address
0x480B C5D0
Instance
ISP_CCP2
Description
Control register for the memory channel. It defines the data format of the source frame stored in
memory and how this frame is processed.
Type
RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
RESERVED
CHAN_EN
DST_PACK
DST_PORT
SRC_PACK
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
BURST_SIZE
DST_FORMAT
SRC_FORMAT
READ_THROTTLE
1366
Camera Image Signal Processor
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated