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26-8.
Overall Booting Sequence
............................................................................................
26-9.
Booting Device List Setup
.............................................................................................
26-10. Common Peripheral Booting Protocol
...............................................................................
26-11. Peripheral Booting Procedure
........................................................................................
26-12. Customer USB Descriptor Selection
.................................................................................
26-13. Fast External Boot Procedure
........................................................................................
26-14. Memory Booting Procedure
...........................................................................................
26-15. Detailed Memory Booting for Non-XIP Booting Devices
..........................................................
26-16. NAND Device Detection
...............................................................................................
26-17. NAND ID2 Detection
...................................................................................................
26-18. Bad NAND Invalid Block Detection
..................................................................................
26-19. ECC Locations in NAND Spare Areas
...............................................................................
26-20. ECC Locations in 4-KB Page NAND Spare Areas
.................................................................
26-21. MLC NAND Data Encoding
...........................................................................................
26-22. MLC NAND Page Layout
..............................................................................................
26-23. OneNAND/Flex-OneNAND Read Sector
............................................................................
26-24. MMC/SD Booting
.......................................................................................................
26-25. TWL5030 Connectivity Constraints to Support MMC/SD/eMMC/eSD Booting on SD/MMC Port 1 and
SD/MMC Port 2
.........................................................................................................
26-26. TWL5030 Connectivity Constraints to Support eMMC/eSD Booting on SD/MMC Port 1
.....................
26-27. TWL5030 Connectivity Constraints to Support eMMC/eSD Booting on SD/MMC Port 2
.....................
26-28. MMC/SD Detection Procedure
........................................................................................
26-29. SD/MMC Booting
.......................................................................................................
26-30. MBR Detection Procedure
.............................................................................................
26-31. Get MBR Partition
......................................................................................................
26-32. Image Format
...........................................................................................................
26-33. CH Format
...............................................................................................................
26-34. CONTROL_SAVE_RESTORE_MEM Format
......................................................................
27-1.
Debug and Emulation Hardware in the Device
.....................................................................
27-2.
ICEPick Overview
......................................................................................................
27-3.
ICEPick Overview
......................................................................................................
27-4.
TAP State Transitions
..................................................................................................
27-5.
Multiple Read in ROUTER Instruction
...............................................................................
27-6.
Multiple Write in ROUTER Instruction
...............................................................................
27-7.
Mixed Read and Write in ROUTER Instruction
.....................................................................
27-8.
SDTI in the Device
.....................................................................................................
27-9.
SDTI Connected in Four Data Pins Mode
...........................................................................
27-10. SDTI Connected in Two Data Pins Mode
...........................................................................
27-11. SDTI Connected in One Data Pin Mode
............................................................................
27-12. Dual-Edge Clock Waveform
...........................................................................................
27-13. Single-Edge Clock Waveform
.........................................................................................
27-14. SDTI Integration
........................................................................................................
27-15. SDTI Block Diagram
...................................................................................................
27-16. EPM Overview
..........................................................................................................
27-17. EPM Control Access
...................................................................................................
A-1.
OMAP36xx in CYN Package Block Diagram
.......................................................................
A-2.
External Clock Interface
...............................................................................................
A-3.
Camera Subsystem Block Diagram
..................................................................................
A-4.
Display Subsystem Block Diagram
...................................................................................
77
SWPU177N – December 2009 – Revised November 2010
List of Figures
Copyright © 2009–2010, Texas Instruments Incorporated