Display subsystem
RFBI
DISPC
L3
interconnect
Registers
Registers
L4 interface
L4
interconnect
LCD data
24
LCD up to 24-bit
parallel output
Configuration, data
Configuration
Status
PLL control
DSI protocol
engine
DSI complex I/O
DSI PLL
controller
DSI PLL
Registers
Configuration,
data
Data
Control
LCD serial
output
a3621-007
LCD data
Public Version
www.ti.com
Interconnect
A.6.3 Display Subsystem Functional Description
is a schematic of the modules available modules in the display subsystem for the OMAP36xx
in CYN package devices.
Figure A-4. Display Subsystem Block Diagram
A.6.4 Display Subsystem Use Guidelines
The DISPC digital (video encoder) data path must be kept disabled (DIGITALENABLE of
DISPC_CONTROL[1] = 0x0). Moreover, to avoid current leakage, the following bits must be set to 0:
•
DSS.DSS_CONTROL[5] DAC_POWERDN_BGZ
•
VENC_OUTPUT_CONTROL[2:0]
•
PRCM.CM_FCLKEN_DSS[2] EN_TV
•
CONTROL.CONTROL_DEVCONF[18] TVOUTBYPASS
A.7
Interconnect
NOTE:
This subsection provides a quick reference about the unavailable modules in Interconnect
aspects. Cells highlighted in orange in the tables indicate modules with removed functionality
in the OMAP36xx in CYN package devices. These modules are still present on the die,
therefore their mappings are provided to control their activity and for debug purposes.
3667
SWPU177N – December 2009 – Revised November 2010
OMAP36xx Multimedia Device in CYN Package
Copyright © 2009–2010, Texas Instruments Incorporated
