SDTI
Device
sdti-007
SDTI_FCLK
SDTI_ICLK
SDTI_RST
reset
Interface clock
Functional clock
PRCM
L4_EMU_FCLK
L4_EMU_ICLK
EMU_RSTPWRON
L4 EMU
Public Version
www.ti.com
SDTI Module
Table 27-31. CPU2 Message
Description
Format
Header
110D DA00
Address
A = 1
A = 0
Ad[7:0]
Nonexistent field
Data
DD = 00
DD = 01
DD = 10
Da[7:0]
Da[15:8]
Da[31:24]
Da[23:16]
Da[7:0]
Da[15:8]
Da[7:0]
27.3.3 SDTI Integration
shows the internal connections between the SDTI and other modules in the device.
Figure 27-14. SDTI Integration
27.3.3.1 Clocking and Reset
27.3.3.1.1 Clocks
The SDTI receives two clocks:
•
SDTI_ICLK: The L4_EMU clock for the interface and the functional clock for SDTI
•
SDTI_FCLK: The serial interface base clock, which is always twice as fast as SDTI_ICLK
Trace serial interface (sdti_clk) runs on a clock generated in SDTI. The serial interface clock is derived
from SDTI_FCLK in programmable clock divider.
Divider factors for serial clock generation are referenced to SDTI_ICLK. These factors range from 1 to 10.
SDTI_FCLK always has an internal clock that runs twice as fast as the serial clock selected through
division factors, which is used as a base clock in dual-edge serial transmitters.
27.3.3.1.2 Reset
The SDTI is reset with hardware POR. All SDTI registers are asynchronously reset. The SDTI remains
operational and with its setup preserved when a warm reset is triggered to export the trace history to the
trace controller. This trace history may contain key information from a debug perspective for
understanding the root cause of the warm reset.
The PRCM module delivers the EMU_RSTPOWRON reset qualifier and the RESET signal to distinguish
power on from a warm (soft) reset.
The application or debugger software can reset the SDTI at any time by writing 1 to the
[1] SOFTRESET bit. This puts the SDTI in the same reset state as a hardware reset.
3611
SWPU177N – December 2009 – Revised November 2010
Debug and Emulation
Copyright © 2009–2010, Texas Instruments Incorporated
