icepick-004
test logic reset
run test idle
select DR scan
select IR scan
capture DR
capture IR
shift DR
shift IR
exit1 DR
exit1 IR
pause DR
pause IR
exit2 DR
exit2 IR
update DR
update IR
TMS=0
TMS=1
TMS=1
TMS=1
TMS=1
TMS=0
TMS=0
TMS=0
TMS=0
TMS=0
TMS=0
TMS=1
TMS=1
TMS=0
TMS=0
TMS=1
TMS=1
TMS=0
TMS=0
TMS=0
TMS=1
TMS=1
TMS=0
TMS=0
TMS=1
TMS=1
TMS=1
TMS=0
TMS=0
TMS=1
TMS=1
TMS=1
Public Version
ICEPick Module
www.ti.com
27.2.4.2 ICEPick Secondary Debug TAPs
shows the secondary debug TAPs connected to the ICEPick scan chain. The TAP number
shows the position of the TAP in the scan chain and the SDTRj register (see
) used to get
access to control and status for this TAP. The ICEPick internal TAP can also be referenced as the primary
TAP; it is always in the first position in the scan chain (ICEPick TAP input is connected to the device
jtag_tdi pin).
Table 27-2. Secondary Debug TAP Mapping
Secondary
CoreSight
TAP No.
Modules Accessed Through That JTAG Port
JTAG port
D2D
No
0
Die-to-die interface
IVA
No
1
C64x+/ICEMaker
ARM968™
No
2
ARM968/ICECrusher™ – IVA Sequencer
DAP
Yes
3
MPU/ICECrusher – CS / ETM11 / PSA
Yes
ETB
Yes
SDTI
No
Clocks Management
→
L3
→
L4_CORE
No
Power Management
→
L4_EMU
→
L4_WKUP
Reserved
No
4–15
Reserved
27.2.4.3 ICEPick TAP states
The TAP consists of:
•
32-bit device ID register
•
1-bit bypass register
•
6-bit instruction register (IR)
shows ICEPick TAP states. In the figure, TMS corresponds to the jtag_tms input pin.
Figure 27-4. TAP State Transitions
3590
Debug and Emulation
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated