SDTI
EPM
TPIU
ETB
IVA2
MPU
C64x+
Core
Video
seq
ETM
DAP
ICECrusher
ICEPick
L4 EMU
L3 access
Triggers
JTAG
JTAG
Debug emulation
Device
Trace
port
EMU
pin
JTAG
debug-001
Public Version
Debug and Emulation Overview
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27.1 Debug and Emulation Overview
This chapter presents an overview of the debug and emulation hardware features.
27.1.1 Debug and Emulation Overview Features
Debugging a system containing multiple embedded processors involves an environment that connects
high-level debugging software, executing on a host computer, to a low-level debug interface supported by
the device. Between these levels is an emulator, which facilitates communication between the host
debugger and the emulation logic on the device.
Debug and emulation is a combination of hardware and software that connects the host debugger to the
target device. It uses one or more hardware interfaces and/or protocols to convert actions dictated by the
debugger user to JTAG commands and scans that execute the core hardware.
shows the module used in the device for debug and emulation.
Figure 27-1. Debug and Emulation Hardware in the Device
The debug software and hardware components lets the user control multiple central processing unit (CPU)
cores embedded in the device in a global or local manner. This environment provides:
•
Synchronized global starting and stopping of multiple processors (the ICEPick™ feature is not
supported by all the platform processors)
•
Starting and stopping of an individual processor
•
Each processor can generate triggers that can be used to alter the execution flow of other processors.
27.1.2 Debug and Emulation Functional Description
27.1.2.1 ICEPick
The device contains multiple processors, each of which has a JTAG test access port (TAP) embedded in
the processor. The ICEPick module manages these TAPs and the power, clock, and reset controls for the
module that has the TAP. At its root, ICEPick is a scan path linker that allows the scan controller to
selectively choose which subsystem TAPs are accessible through the device level debug port. ICEPick is
configured through its IEEE 1149.1 JTAG TAP controller.
The ICEPick module is described in
, ICEPick Module.
3586
Debug and Emulation
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated