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General-Purpose Memory Controller
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10.1.5.3.10 Bus Keeping Support
At the end-cycle time of a read access, if no other access is pending, the GPMC drives the bus with the
last data read after RDCYCLETIME completion time to prevent bus floating and reduce power
consumption.
After a write access, if no other access is pending, the GPMC keeps driving the data bus after
WRCYCLETIME completes with the same data to prevent bus floating and power consumption.
10.1.5.4 WAIT Pin Monitoring Control
GPMC access time can be dynamically controlled using an external gpmc_wait pin when the external
device access time is not deterministic and cannot be defined and controlled only using the GPMC internal
RDACCESSTIME, WRACCESSTIME and PAGEBURSTACCESSTIME wait state generator.
The GPMC four input wait pins: gpmc_wait3, gpmc_wait2, gpmc_wait1, and gpmc_wait0. These four pins
allow direct plugin and control of external devices with different wait-pin polarity. They also allow the
overlap of wait-pin assertion from different devices without affecting access to devices for which the wait
pin is not asserted.
•
The GPMC.
[17:16] WAITPINSELECT field (i = 0 to 7) selects which input
gpmc_wait pin is used for the device attached to the corresponding chip-select.
•
The polarity of the wait pin is defined through the WAITxPINPOLARITY bit of the
GPMC.
register. A wait pin configured to be active low means that low level on the
WAIT signal indicates that the data is not ready and that the data bus is invalid. When WAIT is
inactive, data is valid.
The GPMC access engine can be configured by CS to monitor the wait pin of the external memory device
or not, based on the access type: read or write.
•
The GPMC.
[22] WAITREADMONITORING bit defines whether the wait pin should
be monitored during read accesses or not.
•
The GPMC.
[21] WAITWRITEMONITORING bit defines whether the wait pin should
be monitored during write accesses or not.
The GPMC access engine can be configured to monitor the wait pin of the external memory device
asynchronously or synchronously with the GPMC_CLK clock, depending on the access type: synchronous
or asynchronous (the GPMC.
WRITETYPE bits).
10.1.5.4.1 Wait Monitoring During an Asynchronous Read Access
When wait-pin monitoring is enabled for read accesses (WAITREADMONITORING), the effective access
time is a logical AND combination of the RDACCESSTIME timing completion and the wait-deasserted
state.
During asynchronous read accesses with wait-pin monitoring enabled, the wait pin must be at a valid level
(asserted or deasserted) for at least two GPMC clock cycles before RDACCESSTIME completes, to
ensure correct dynamic access-time control through wait-pin monitoring. The advance pipelining of the two
GPMC clock cycles is the result of the internal synchronization requirements for the WAIT signal.
In this context, RDACCESSTIME is used as a WAIT invalid timing window and is set to such a value that
the wait pin is at a valid state two GPMC clock cycles before RDACCESSTIME completes.
Similarly, during a multiple-access cycle (for example, asynchronous read page mode), the effective
access time is a logical AND combination of PAGEBURSTACCESSTIME timing completion and the
wait-deasserted state. Wait-monitoring pipelining is also applicable to multiple accesses (access within a
page).
•
WAIT monitored as active freezes the CYCLETIME counter. For an access within a page, when the
CYCLETIME counter is by definition in a lock state, WAIT monitored as asserted extends the current
access time in the page. Control signals are kept in their current state. The data bus is considered
invalid, and no data are captured during this clock cycle.
2134
Memory Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
