Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 1845 / 3738

Public Version
www.ti.com
Display Subsystem Register Manual
Table 7-179. Register Call Summary for Register DISPC_GFX_SIZE
Display Subsystem Basic Programming Model
• Display Controller Basic Programming Model : [0]
• Graphics Layer Configuration Registers : [1]
• Graphics Window Attributes : [2] [3]
• Rotation/Mirroring Registers : [4]
Display Subsystem Register Manual
• Display Controller Register Mapping Summary : [5]
Table 7-180. DISPC_GFX_ATTRIBUTES
Address Offset 0x0A0
Physical address 0x4805 04A0 Instance DISC
Description The register configures the graphics attributes.
Shadow register, updated on VFP start period or EVSYNC.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED GFXFORMAT
RESERVED
GFXENABLE
GFXROTATION
GFXBURSTSIZE
GFXENDIANNESS
GFXNIBBLEMODE
GFXARBITRATION
GFXCHANNELOUT
GFXFIFOPRELOAD
GFXSELFREFRESH
PREMULTIPLYALPHA
GFXREPLICATIONENABLE
Bits Field Name Description Type Reset
31:29 Reserved Write 0s for future compatibility. RW 0x000000
Read returns 0.
28 PREMULTIPLYALPHA The field configures the DISPC GFX to process incoming data as RW 0
pre-multiplied alpha data or non premultiplied alpha data.
Default setting is non pre-multiplied alpha data.
0x0: Non pre-multiplyalpha data color component
0x1: Pre-multiplyalpha data color component
NOTE: The pre-multiplied alpha option is
only valid when bit field [4:1]
GFXFORMAT is set to ARGB or
RGBA formats. Otherwise, the
PREMULTIPLYALPHA bit field is
ignored by the hardware.
27:16 Reserved Write 0s for future compatibility. RW 0x000000
Read returns 0.
15 GFXSELFREFRESH Enables the self refresh of the graphics window from its own FIFO RW 0
only.
0x0: The graphics pipeline accesses the interconnect to fetch
data from the system memory
0x1: The graphics pipeline does not need anymore to fetch
data from memory. Only the graphics FIFO is used. It
takes effect after the frame has been loaded in the FIFO
14 GFXARBITRATION Determines the priority of the graphics pipeline. The graphics RW 0
pipeline is one of the high priority pipeline. The arbitration wheel
gives always the priority first to the high priority pipelines using
round-robin between them. When there is only normal priority
pipelines sending requests, the round-robin applies between them.
1845 SWPU177N – December 2009 – Revised November 2010 Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated