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IVA2.2 Subsystem Functional Description
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5.3.1.7.1 Event Type
The interrupt controller provides three types of interrupt sources to the DSP CPU:
•
Single event
–
A single system event can be directly routed to a CPU interrupt input.
–
A dropped system event is supported through the CPU dropped interrupt reporting mechanism; that
is, if the CPU misses the interrupt input, the system event is missed.
•
Combined event
–
Up to four event combiners
–
Each combiner allows up to 32 system events to be logically ORed into a single event that can be
routed to the DSP CPU.
•
Exception event: This event is considered a single event, but it is directly connected to the exception
input of the DSP CPU.
5.3.1.7.2 Event Behavior
•
Single event source: The interrupt selector routes 1 of 124 events to a DSP CPU interrupt, as
programmed in the interrupt selector registers (IC.
registers (where j is 1 to 3). Logic in the
CPU and the INTC combine to detect instances where an interrupt request is asserted before an
earlier interrupt request was serviced. The INTC records the interrupt number of the first interrupt and
keeps this information until directed to release the interrupt, either through reset or by application
software. This record can be used as an additional system event to notify the application of an interrupt
failure. Interrupts that qualify for dropped detection are defined through an IDROP mask that sets the
IC.
register. The masked IDROP event output (EVT96; see
) is available as a system event that can be selected as either a
DSP CPU interrupt or an exception event.
•
Combined source: The event combiners create a combined event from the logical OR of 32
system-event flags qualified by a mask provided through programmable registers (IC.
where i = 0 to 3). The combination of the event flags creates an event that is asserted when any of the
event flags included in its generation is active. Software must clear the event flags (IC.
where
i = 0 to 3) to deassert a combined event.
NOTE:
The use of event flags makes it impossible for the CPU to detect the dropping of
independent system events; therefore, dropped interrupt capability is not directly supported
for combined events.
The interrupt event combiners create four shared interrupt sources:
–
EVT0: Logical OR of
[31:04] (i = 0) masked by
[31:04] (i = 0)
–
EVT1: Logical OR of
[63:32] (i = 1) masked by
[63:32] (i = 1)
–
EVT2: Logical OR of
[95:64] (i = 2) masked by
[95:64] (i = 2)
–
EVT3: Logical OR of
[127:96] (i = 3) masked by
[127:96] (i = 3)
are the event flag registers and
are the event mask registers. These combined
events are presented to the interrupt selection logic.
•
Exception event source: As with the event combiner, the exception combiner allows multiple system
events to be grouped as a single event input to the CPU, and the combiner provides mask registers to
remove undesirable events. Because only one exception is input to the CPU, all mask registers work
together to combine up to 128 events as a single EXCEP output. This lets the CPU service all
available system exceptions.
The shared exception source is created as follows:
EXCEP: Logical OR of EF[127:04] masked by XM[127:04]
Where EF[i * 32 + j] =
[j] and XM[i * 32 + j] =
[j] (i = 0, 1, 2, 3 and j = 0 to 31).
The logic is similar to that of the event combiners, except that only one combined event is routed to
EXCEP.
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IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
