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SDMA Functional Description
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Table 11-8. Logical DMA Channel Events
Event
Description
End of packet
A packet transfer completed.
End of block
A block transfer completed.
End of frame
A frame transfer completed.
End of super block
A super block transfer completed.
Half of frame
Half of the current frame transferred.
Start of last frame
The first element of the last frame transferred.
Transaction error
A transaction error returned by the interconnect in either the read or write port.
Address error
An attempt was made to perform a DMA access to an address not aligned on an ES boundary.
Condition to occur: if DMA4_CEN[23:0] CHANNEL_ELMNT_NBR = 0x000000 or
DMA4_CFN[15:0] CHANNEL_FRAME_NBR = 0x0000 or DMA4_CSDP[1:0] DATA_TYPE =
0x3.
Supervisor transaction error
An error occurred, for example, when an unauthorized initiator (that is not a supervisor ) tries to
use a supervisor transfer.
Drain end
Drain is completed (
[10] WR_ACTIVE becomes 0).
Drop error
A drop event interrupt is generated when a DMA request is being serviced while a second one
is asserted and a third one arrives before the second DMA request is serviced.
The logical DMA channels that generate an interrupt on a particular IRQ output are specified through the
register (where j is the IRQ number: 0, 1, 2, or 3). The events that generate an
interrupt for a particular channel can be configured through the channel
register.
When an interrupt is detected, the logical DMA channel generating the event can first be identified by
reading the
register. The event causing the interrupt then can be identified by
reading the interrupt status via the relevant DMA channel
register.
11.4.13 Packet Synchronization
A packet transfer notion is related to the behavior of some peripheral, which have certain buffering
capability and requires to transfer the buffer content once an element number threshold is reached (a
hardware DMA request is generated). To associate a frame synchronization to each DMA request is
possible, but this limits the maximum transfer size. Indeed the maximum transfer size is proportional to the
FIFO depth of the peripheral:
maximum_transfer_size =peripheral_FIFO_depth x number_of_frame_in_block.
The packet synchronization allows to dissociate the transfer size from the FIFO depth of the peripheral.
Only Constant addressing mode is allowed on RD port or WR port if source target or destination target is
packet synchronized respectively.
Example:
Let's consider a camera interface, which have a FIFO_depth of 128 Words and a
FIFO_element_number_threshold of 128 and a picture to transfer with a size 320 lines per 240 columns. If
frame synchronization is associated to each DMA request then the maximum transfer size that can be
performed is 128x2
16
words. In this case, a frame is 128 words long, which does not fit the size of a line.
Then it's not possible to generate an interrupt at the end of line. However with introducing the packet
transfer notion, which is related to the peripheral FIFO behavior/structure, the maximum transfer size
(maximum_transfer_size = 2
24
x 2
16
words) is independent of both peripheral_FIFO_depth and
FIFO_element_number_threshold. This allows, making an enough long transfer within one channel
context and perform rotation operation on big image format.
The main features of DMA Packet transfer are as follows:
•
DMA
Packet_Data_Size
for
each
DMA
Request:
typically
this
will
be
Peripheral_element_number_threshold Number of elements in a packet shares the
and
configuration registers. Indeed if the peripheral is the source target, respectively
destination target, that means the used addressing mode is constant, consequently
respectively DMA4_CDFI[15:0], is used to specify the packet data size (PKT_ELNT_NBR) and the bit
fields [31:16] are unused. To specify the Packet data size in the
or
, the
user must set the
[24] SEL_SRC_DST_SYNC respectively to 1 or 0.
2358
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
