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ICEPick Module
27.2.4.5.3.2 ICEPICKCODE Instruction
Description: The ICEPICKCODE instruction specifies that the DR shift path is 32 bits long. This path
provides a way to export the ICEPick identification (IPID) register (see
). The IPID register is a
32-bit register that specifies the features and version of ICEPick. This ID register is for the ICEPick module
and should not be confused with the ID register for the device or any other module. The use of this
instruction has no effect on the operation of the on-chip system logic.
Capture DR state: The 32-bit ICEPick code is loaded into the data shift register during the Capture DR
state.
Shift DR state: The value captured is shifted out during the Shift DR TAP state with the LSB first, while
the value of jtag_tdi is shifted into the MSB of the data shift register. Data is shifted from the MSB to the
LSB.
Update DR state: The shifted in data is ignored in the Update DR state.
27.2.4.5.3.3 USERCODE Instruction
Description: The USERCODE instruction specifies that the DR shift path is 32 bits long. This path
provides a way to export the value of the user code (UC) register (see
). The UC register is a
32-bit register that specifies the variant of a device. The use of this instruction has no effect on the
operation of the on-chip system logic.
Capture DR state: The 32-bit UC register in the device is loaded into the data shift register during the
Capture DR state.
Shift DR state:The value captured is shifted out during Shift DR TAP state with the LSB first, while the
value of jtag_tdi is shifted into the MSB of the data shift register. Data is shifted from the MSB to the LSB.
Update DR state:The shifted-in data is ignored in the Update DR state.
27.2.4.5.3.4 BYPASS Instruction
Description:The IEEE 1149.1 specification mandates a BYPASS instruction and that the instruction
decode must be an all-ones value equal in length to the instruction register length. All unused TAP
controller instruction codes default to having the same characteristics as the BYPASS instruction.
The BYPASS instruction, and all instruction codes defaulting to the BYPASS instruction, specifies a DR
shift path 1 bit long between the ICEPick TDI and TDO. This path provides a way to export the 0 used to
differentiate bypass data from the data in the device ID register, if a DR scan is performed immediately
following the Test Logic Reset TAP state.
Capture DR state: In the Capture DR state, 0 is loaded into the 1-bit shift path selected by this
instruction.
Shift DR state: When the BYPASS instruction is the current instruction in the instruction register, serial
data is transferred from TDI to TDO through the 1-bit bypass register while in the Shift DR state with a
delay of one TCK cycle.
Update DR state: The shifted-in data is ignored in the Update DR state.
The BYPASS instruction is used when a scan controller wants to shift in data or commands to another
TAP on the scan path without disturbing this TAP.
27.2.4.5.3.5 CONNECT_PUBLIC Instruction
Description: The CONNECT_PUBLIC instruction, in combination with the connect register, is used to
enable many of the other IR instructions. Before being enabled, the instructions act as the BYPASS
instruction.
The CONNECT_PUBLIC instruction specifies that the DR shift path is 8 bits long. This path provides a
way to access the connect register, which is described in
Capture DR state: When the CONNECT instruction is in the IR, a DR scan scans through the 8 lower bits
of the data shift register. Bit 7 is not part of the connect register (0 is used to read the register; 1 is used to
write the register).
3593
SWPU177N – December 2009 – Revised November 2010
Debug and Emulation
Copyright © 2009–2010, Texas Instruments Incorporated
