memmap-002
IVA2.2 DSP
L1P cache
allocated
SRAM
L1D cache
allocated
SRAM
L2 RAM
cache
SDRAM
(connected through the
SDRC)
L1P memory-
mapped
SRAM
L1D memory-
mapped
SRAM
L1P RAM
L1D RAM
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IVA2.2 Subsystem Memory Space Mapping
Figure 2-2. IVA2.2 Subsystem Memory Hierarchy
2.4.1.2
IVA2.2 Cache Allocation
After reset, the L1P RAM is used as a 32-KB memory-mapped RAM. The L1P RAM can be programmed
in the C64x+ ™ DSP program memory controller to allocate 0 (default), 4, 8, 16, or 32KB to cache. When
32KB are allocated to cache, there is no more memory-mapped L1P.
After reset, the L1D RAM is used as an 80-KB memory-mapped RAM. The L1D RAM can be programmed
in the C64x+ DSP data memory controller to allocate 0 (default), 4, 8, 16, or 32KB to cache. When 32KB
are allocated to cache, 48KB are still allocated to the memory-mapped L1D.
After reset, L2 is used as a 96-KB memory-mapped RAM. L2 can be programmed to allocate 0 (default),
32, or 64KB to cache. When 64KB are allocated to cache, 32KB are still allocated to memory-mapped L2.
is an example of the L1D RAM cache allocation, where 16KB are allocated to cache.
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SWPU177N – December 2009 – Revised November 2010
Memory Mapping
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