Public Version
SDMA Register Manual
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Bits
Field Name
Description
Type
Reset
20:19
SYNCHRO_CONTROL_
Channel Synchronization control upper (used in
RW
0x0
UPPER
conjunction with the 5 bits of synchro channel
Used in conjunction, as two msb, with the five bits of the
synchro channel bit field.
18
BS
Block synchronization
RW
0x-
This bit used with the fs to see how the DMA request is
serviced in a synchronized transfer
17
TRANSPARENT_COPY_
Transparent copy enable
RW
0x-
ENABLE
0x0: Transparent copy mode is disabled
0x1: Transparent copy mode is enabled
16
CONST_FILL_ENABLE
Constant fill enable
RW
0x0
0x0: Constant fill mode is disabled
0x1: Constant fill mode is enabled
15:14
DST_AMODE
Selects the addressing mode on the Write Port of a
RW
0x-
channel.
0x0: Constant address mode
0x1: Post-incremented address mode
0x2: Single index address mode
0x3: Double index address mode
13:12
SRC_AMODE
Selects the addressing mode on the Read Port of a
RW
0x-
channel.
0x0: Constant address mode
0x1: Post-incremented address mode
0x2: Single index address mode
0x3: Double index address mode
11
RESERVED
Reserved. Write 0s for future compatibility. Read returns
RW
0x0
0.
10
WR_ACTIVE
Indicates if the channel write context is active or not
R
0x0
0x0: Channel is not active on the write port
0x1: Channel is active on the write port
9
RD_ACTIVE
Indicates if the channel read context is active or not
R
0x0
0x0: Channel is not active on the read port
0x1: Channel is currently active on the read port
8
SUSPEND_SENSITIVE
Logical channel suspend enable bit
RW
0x0
0x0: The channel ignores the MSuspend even if
EMUFree is set to 0.
0x1: If EMUFree is set to 0 and MSuspend comes in then
all current OCP services (single transaction or burst
transaction as specified in the corresponding CSDP
register) have to be completed before stopping
processing any more transactions
7
ENABLE
Logical channel enable. It is SW responsibility to clear the
RW
0x0
CSR register and the IRQSTATUS bit for the different
interrupt lines before enabling the channel.
0x0: The logical channel is disabled
0x1: The logical channel is enabled
6
READ_PRIORITY
Channel priority on the read side
RW
0x0
0x0: Channel has low priority on the Read side during the
arbitration process
0x1: Channel has high priority on read sided during the
arbitration process
2386
SDMA
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated