Public Version
www.ti.com
SCM Functional Description
13.4.11.4 Basic Programming Model
13.4.11.4.1 SSC Configuration
The configuration of the spreading feature is not mandatory when programming the DPLL. This feature is
usually enabled when the DPLL clocks generate harmonics that can potentially interfere with the GSM
carrier frequencies.
Let's take the SSC featured ADPLL in the CORE domain and try to set the output frequency to
Fout=f
c
=160 MHz . The frequency of the input clock source for CORE ADPLL is Finp=38.4 MHz.
1. The desired output frequency can be achieved with the following ratio of the divider coefficients: (M /
M2)*1/(N+1) = Fout / Finp = 160 / 38.4 = 25 / 6. The dividers used in the CORE ADPLL can be set
within the following ranges: N = 0..127; M = 0..2047 ; M2 = 1;2 . The desired output frequency is
achieved through the following choice of possible divider values: M = 25 ; N = 2 and M2 = 2. In that
case the reference clock Fref = Finp / (N+1) = 38.4 / 3 = 12.8 MHz.
The feedback divider value M = 25 is chosen to satisfy the restriction from
. If, for
example, the deviation
Δ
M / M =
Δ
f / Fc= 0.01 (1%) is chosen, we have M < 2045 / 1.01 and at the
same time M> 20 / 0.99 =20.2.
Once the clock generation control registers are configured, it is possible to configure the spreading on
the clock signal.
2. Calculate the ratio between central(output) frequency and modulation frequency on the base of the
desired peak power reduction, PPR and chosen relative deviation
Δ
f / Fout , where
Δ
f / Fout = f
m
/ f
c
*
10 ^ (PPR/10). To achieve PPR = 10dB with SSC deviation chosen to be equal to 1 percent, the ratio
f
m
/ f
c
=0,001 is needed; hence, f
m
= 0,001* f
c
=0,001 * 160 MHz = 160 KHz. To check whether the
modulation frequency has the appropriate value, check whether it is within the DPLL loop bandwidth or
if fm < Fref / 70 = 12.8 / 70 = 182.86 KHz, which is true.
3. Calculate the contents of the CONTROL.CONTROL_X_DPLL_SPREADING_FREQ[6:0]
R_X_MOD_FREQ_MANT and CONTROL.CONTROL_X_DPLL_SPREADING_FREQ[9:7]
R_X_MOD_FREQ_EXP bit fields on the base of ModFreqDivider value: ModFreqDivider = Fref /
(4*fm)= 12.8 / 4*0.16 = 20 = 20*2^0. This means we should write R_X_MOD_FREQ_EXP=0x0 and
R_X_MOD_FREQ_INT=0x14.
4. The DeltaMStep parameter is calculated according to the formula:
DeltaM=
Δ
M / ModFreqDivider.
On the other side
Δ
M = M * (
Δ
f / f
c
) , hence, parameter DeltaM = M * (
Δ
f / f
c
) / ModFreqDivider =
0.01*25 /20=0.0125 .
In this case write 0x0 in CONTROL.CONTROL_X_DPLL_SPREADING_FREQ[29:28]
R_DSS_DELTA_M_INT bit field. To express the fractional part 0.0125 as a binary, calculate: 0.0125 *
2^18 = 3276.8 , then round to 3277, convert the integer part to binary and write it into the field:
CONTROL.CONTROL_X_DPLL_SPREADING_FREQ[27:10] R_DSS_DELTA_M_FRACT =
0b000000110011001101
5. The spreading must be enabled using the CONTROL.CONTROL_X_DPLL_SPREADING[4]
R_X_SPREADING_ENABLE bit.
NOTE:
It is necessary to configure the spreading on a clock carefully to avoid adding noise on
frequencies that are used by another module. For example, adding spreading on a clock to
reduce noise on GSM frequencies can "move" the generated noise to the frequency of the
memory controller and degrade its performance.
The state of the modulation feature can be monitored with the R_X_SPREADING_ENABLE_STATUS bit
of the corresponding register.
2529
SWPU177N – December 2009 – Revised November 2010
System Control Module
Copyright © 2009–2010, Texas Instruments Incorporated