Texas Instruments OMAP36 Series, Technical Reference Manual

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Camera ISP Basic Programming Model
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– PRV_RADR_OFFSET
– PRV_DSDR_ADDR
– PRV_DRKF_OFFSET
– PRV_WSDR_ADDR
– PRV_WADD_OFFSET
• Busy-writable registers: These registers/fields can be read or written even if the module is busy.
Changes to the underlying settings occur instantaneously.
The busy-writable registers are:
– PRV_WB_DGAIN
– PRV_WBGAIN
• Busy-lock registers:
– All registers EXCEPT the shadow and busy-writable registers belong to this category. Busy-lock
registers cannot be written when the module is busy. Writes are allowed, but no change occurs in
the registers (blocked writes from hardware perspective, but allowed writes from software
perspective).
– After the PRV_PCR [1] BUSY bit is reset to 0, busy-lock registers can be written.
– The PRV_SET_TBL_DATA register cannot be read when the preview engine is busy, because this
register is mapped to memories internally. Such reads return indeterminate data. Byte enables are
not implemented for reading preview engine memories.
The ideal procedure for changing the preview engine registers is:
IF ( PRV_PCR [1] BUSY == 0) OR IF
(EOF interrupt occurs)
DISABLE PREVIEW ENGINE
CHANGE REGISTERS
ENABLE PREVIEW ENGINE
6.5.7.5 Camera ISP Preview Interframe Operations
Between frames, it may be necessary to enable/disable functions or modify memory pointers. Because the
PRV_PCR register and memory pointer registers are shadowed, these modifications can occur any time
before the end of the frame, and the data is latched in for the next frame. The MPU subsystem can
perform these changes on receiving an interrupt.
6.5.7.6 Camera ISP Preview Summary of Constraints
The following is a list of register configuration constraints to adhere to when programming the preview
engine. It can be used as a quick checklist. More detailed register setting constraints can be found in the
individual register descriptions.
• A frame can only be read from memory when the SBL read port is affected to the PREVIEW module
(
ISP_CTRL [27] SBL_SHARED_RPORTA = 0)
• The shading compensation feature can only be used when the SBL read port is affected to the
PREVIEW module (
ISP_CTRL [28] SBL_SHARED_RPORTB = 0)
• If the memory output port is enabled, the memory output line offset and address should be on 32-byte
boundaries.
• The output width must be less than or equal to 4096.
• The output width must be even.
• Input to the horizontal median filter must be even.
• Defect correction can only be used when noise filter is enabled
• Input height must be smaller than CCDC output height.
• The input width of the preview engine must be a multiple of the average count multiplied by the least
common multiple of the odd distance and even distance of the averager.
– ( PRV_HORZ_INFO [13:0] EPH - PRV_HORZ_INFO [29:16] SPH + 1) MOD ((1 << PRV_AVE [1:0]
1284 Camera Image Signal Processor SWPU177N – December 2009 – Revised November 2010
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