dss-203
÷
÷
÷
ø
ö
ç
ç
ç
è
æ
ú
ú
ú
û
ù
ê
ê
ê
ë
é
ú
ú
ú
û
ù
ê
ê
ê
ë
é
=
ú
ú
ú
û
ù
ê
ê
ê
ë
é
Bin
Gin
Rin
370
-129
-129
0
256
0
0
0
256
Bout
Gout
Rout
*
*
256
1
=
Rout
256
1
*
=
Gout
256
1
*
è
æ
256 * Gin
=
Bout
256
1
*
è
æ
-129 * Rin + -129 * Gin + 370 * Bin + B_offset
è
æ
è
æ
è
æ
256 * Rin
è
æ
Rin
255
0
0
255
0
128
Gin
0
255
0
255
0
128
Bin
0
0
255
255
0
128
Initial pixel to send to LCD
Rout
255
0
0
255
0
128
Gout
0
255
0
255
0
128
Bout
0
0
255
255
128
184
Resulting pixel on LCD (after CPR correction)
Rout
255
0
0
255
0
128
Gout
0
255
0
255
0
128
Bout
128
128
255
255
128
255
Resulting pixel on LCD (no CPR correction)
Public Version
www.ti.com
Display Subsystem Basic Programming Model
Figure 7-134. Example - Image With and Without CPR (Standard Matrix)
This CPR matrix gives inputs and outputs very close. However, black cannot be corrected because of it's
zero-components. No matter which coefficients are used in the matrix, the result will always be equal to
the offset added by the LCD backlight.
7.5.3.6
TV Set-Specific Control Registers
The following registers define the digital output configuration:
•
DSS.
•
DSS.
•
DSS.
(m=1)
•
DSS.
(m=1)
•
DSS.
The digital output is enabled/disabled by setting/resetting the DSS.
[1] DIGITALENABLE
bit. A valid configuration must be set before the digital output can be enabled.
Perform the initialization sequence as follows:
1. Initialize the video encoder and the display controller configuration registers.
2. Set the DSS.
[6] GODIGITAL bit and the DSS.
[1]
DIGITALENABLE bit to 1.
3. Wait for the first VSYNC pulse signal.
4. Clear the SYNCLOSTDIGITAL interrupt by setting the DSS.
SYNCLOSTDIGITAL bit to 1.
5. Enable the SYNCLOSTDIGITAL interrupt by setting the DSS.
SYNCLOSTDIGITAL bit to 1.
1737
SWPU177N – December 2009 – Revised November 2010
Display Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated