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High-Speed USB OTG Controller
22.1.4.3.1.1 MSTANDBY Deassertion
MSTANDBY is asserted during reset and continues to be 1 after reset. The high-speed USB controller
does not perform master interface transactions until this signal is deasserted. Firmware must follow these
steps to begin normal operations on the master interface bus:
•
Write 0 to the USBOTG.
[0] ENABLEFORCE bit.
•
Put the high-speed USB controller into no-idle mode (USBOTG.
[4:3] SIDLEMODE
field = 0x1) and no-standby mode (USBOTG.
[13:12] MIDLEMODE field = 0x1).
Even though ENABLEFORCE is 0, MSTANDBY remains asserted until the high-speed USB controller
core is out of idle state.
22.1.4.3.2 Transaction Handling
Depending on whether the module is in the host or peripheral mode, an RX endpoint is assigned to IN or
OUT transactions, respectively. Similarly, a TX endpoint is used for IN transactions in the peripheral mode
and for OUT transactions in the host mode. When a transaction is complete, the appropriate endpoint
interrupt is generated (if enabled).
When a transaction is handled through an RX endpoint, the received packet is placed in the RX FIFO, and
the appropriate RX endpoint interrupt is generated. The packet can then be unloaded from the FIFO either
manually (that is, by the MPU) or by the DMA. Although an RX endpoint is always active for a peripheral,
in host mode the transaction must first be initiated by setting the appropriate request flag (REQPKT). This
indicates to the transaction scheduler that there is an active transaction on this endpoint, which requires
an IN token to be sent to the target function.
When a transaction is handled through a TX endpoint, the packet to send is loaded into the TX FIFO
either manually (that is, by the MPU) or by the DMA. The transaction then must be initiated by setting the
appropriate ready flag (TXPKTRDY) to indicate the availability of the new packet. When the packet is
successfully sent (scheduled according to the protocol rules), the appropriate TX interrupt is generated.
22.1.4.4 Optional Features
This section gives a quick overview of the optional features that are available, depending on the endpoint
configuration.
22.1.4.4.1 Double Packet Buffering
When double packet buffering is enabled (by setting the MSB of the FIFOSZ register two data packets can
be stored in the FIFO. This option can be set for both the TX and RX endpoints in both the peripheral and
host mode. For a TX endpoint, double-buffering means that up to two packets can be loaded into the FIFO
awaiting transmission; for an RX endpoint, one packet can be received while another is being read.
Double packet buffering is especially advisable for isochronous transactions to avoid underrun or overrun
errors.
The high-speed USB controller provides dynamic FIFO sizing with an overall RAM size of 16K bytes,
which can then be allocated to the different endpoints when the module is initialized. The maximum size of
an endpoint FIFO is 4096 bytes for single packet buffering and 8192 bytes for double packet buffering.
The firmware must ensure that a block of RAM is properly assigned to all TX and RX endpoints,
considering the total RAM size and the maximum packet size set for the endpoint.
22.1.4.4.2 High-Speed USB OTG Support for Big Endian
In the example in
, the high-speed USB OTG controller module is configured as a USB device
and is connected to a standard USB host. The two interconnect interfaces of the high-speed USB OTG
controller connect it to the system bus. The register read/write is performed through the interconnect slave
interface (control path). The data transfer to/from system memory takes place through the interconnect
master interface (data path).
The data transfer on the USB is always in little-endian mode, but on interconnect it can be in little- or
big-endian mode, as shown in
.
3223
SWPU177N – December 2009 – Revised November 2010
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
Copyright © 2009–2010, Texas Instruments Incorporated
