Texas Instruments OMAP36 Series, Technical Reference Manual

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High-Speed USB OTG Controller
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Table 22-12. OTG_SYSCONFIG
Address Offset 0x0000 0404
Physical Address Instance USBHS
See Table 22-9
Description Standard configuration
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED RESERVED
AUTOIDLE
SIDLEMODE SOFTRESET
MIDLEMODE
ENABLEWAKEUP
Bits Field Name Description Type Reset
31:14 RESERVED reserved R 0x00000
13:12 MIDLEMODE Master interface power management control. Standby/wait control RW 0x0
0x0: Force Standby mode. Mstandby asserted unconditionally
0x1: No standby mode. Mstandby never asserted.
0x2: Smart standby mode. Mstandby asserted when no more
activity on the USB master.
11:5 RESERVED reserved R 0x00
4:3 SIDLEMODE Slave interface power management control. Req/ack control RW 0X0
0x0: Force Idle mode. Sidleack asserted after Midlereq assertion
0x1: No idle mode. Sidleack never asserted.
0x2: SmartIdle mode. Sidleack asserted after Midlereq assertion
when no more activity on the USB.
2 ENABLEWAKEUP Enable wakeup capability RW 0
0x0: Wakeup disabled
0x1: Wakeup enabled
1 SOFTRESET Software reset bit RW 0
0x1: Starts softreset sequence.
0 AUTOIDLE Autoidle bit RW 1
0x0: Clock always running
0x1: When no activity on L3 interconnect, clock is cut off.
Table 22-13. Register Call Summary for Register OTG_SYSCONFIG
High-Speed USB OTG Controller
• Clocking, Reset, and Power-Management Scheme : [0] [1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12]
• Basic Operation : [13] [14]
• Power Management Basic Programming Model : [15] [16] [17] [18] [19] [20] [21] [22] [23] [24] [25] [26] [27] [28] [29] [30] [31]
[32] [33] [34]
• High-Speed USB OTG Controller Registers : [35]
3230 High-Speed USB Host Subsystem and High-Speed USB OTG Controller SWPU177N – December 2009 – Revised November 2010
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