Texas Instruments OMAP36 Series, Technical Reference Manual

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High-Speed USB OTG Controller
– The interface clock(s) USBHS_ICLK are disabled (PRCM register bit
PRCM.CM_ICLKEN1_CORE[4] set to 0) or under automatic control (PRCM register bits
PRCM.CM_ICLKEN1_CORE[4] and PRCM.CM_AUTOIDLE1_CORE[4] both set to 1)
– L4 interface clock idle transitions
Configured in no-idle mode (USBOTG.
OTG_SYSCONFIG [4:3] SIDLEMODE field = 0x1), the
high-speed USB controller module does not go to idle mode and the idle acknowledge is never
sent.
Table 22-5 describes the high-speed USB slave interface power management modes.
Table 22-5. High-Speed USB Slave Interface Power Management Modes
Power Management Mode Requested by the PRCM USBOTG. OTG_SYSCONFIG [4:3] SIDLEMODE Field
Force-idle 0x0
No-idle 0x1
Smart-idle 0x2
Reserved 0x3
NOTE: The high-speed USB controller standby status can be checked by the PRCM module
register bit CM_IDLEST1_CORE[4].
•
0: High-Speed USB is active.
• 1: High-Speed USB is in standby mode.
The high-speed USB controller wake-up status can be checked by the PRCM module
register bit PM_WKST1_CORE[4].
• Read 0: Wakeup has not occurred or was masked.
• Read 1: Wakeup has occurred.
• Write 0: Status bit unchanged.
• Write 1: Status bit is cleared to 0.
22.1.3.1.3.3 Local Power Management
The high-speed USB controller has local power management by internal clock gating features:
• Internal interface clock autogating: Clock for the L3 interconnect logic can be gated when the module is
not accessed, if the USBOTG.
OTG_SYSCONFIG [0] AUTOIDLE bit is set. Otherwise, this logic is
free-running on the interface clock. This bit is used to save power when the module is not used
because of the multiplexing configuration selected at the chip level. This bit has precedence over all
other internal configuration bits.
22.1.3.1.4 Power Domain
The high-speed USB controller is attached to the CORE power domain (see Chapter 3 , Power, Reset, and
Clock Management).
22.1.3.2 Hardware Requests
22.1.3.2.1 Interrupt Requests
Table 22-6 lists the interrupt lines that are driven out from the high-speed USB controller to the MPU
subsystem INTC.
3219 SWPU177N – December 2009 – Revised November 2010 High-Speed USB Host Subsystem and High-Speed USB OTG Controller
Copyright © 2009–2010, Texas Instruments Incorporated