Public Version
High-Speed USB OTG Controller
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22.1.4.2 Configuration
The Mentor Graphics IP RTL MUSBMHDRC can be configured to generate some customized hardware.
Those options are all hard-wired and cannot be reprogrammed in the case of the TI High-Speed USB
controller.
The following options are selected:
•
8-bit internal data path processing width (mandated by the use of ULPI)
•
32-bit vcontrol/vstatus support
•
External charge pump: Hacked
•
Software connect/disconnect supported
•
Little-endian and big-endian byte ordering
•
Eight DMA channels (with internal DMA initiator implemented)
•
Dynamic FIFO sizing enabled
•
16K bytes RAM buffer
•
15 IN/OUT endpoints in addition to control endpoint 0
•
IN/OUT bulk packet splitting/combining enabled
•
High-bandwidth IN/OUT isochronous support enabled (see Universal Serial Bus Specification Revision
2.0)
22.1.4.3 Basic Operation
This section provides an overview of the module basic operation.
To implement the most time-critical functions in hardware, the module provides all of the encoding,
decoding, and checking required to send and receive USB packets-interrupting the MPU only when
endpoint data is successfully transferred. Generally, the following steps are performed:
22.1.4.3.1 Module Initialization
First, the firmware must do the overall initialization of the module by configuring the interrupts, the DMA
controller, and the individual endpoints.
The specific items of a configuration are for each endpoint:
•
Direction TX/RX
•
Speed: High/full/low
•
Special host settings when used in host mode (function address/hub parameters, etc.)
•
Transaction protocol: Control/isochronous/bulk/interrupt
•
Maximum packet size, that can be transferred through the endpoint
•
Whether DMA is required (DMA enable)
•
DMA mode
•
Start address of the endpoint FIFO within the RAM block
•
Maximum packet size allowed
•
Whether double-buffering is required. This and the previous option define the amount of space that
must be allocated to the FIFO. In the case of double-buffering, the FIFO size is doubled; therefore, the
maximum supported size is 8196 bytes for the endpoint FIFOs.
NOTE:
On the system level, it must be ensured that the reset and the interface are selected before
the 60-MHz functional clock (USBHS_FCLK) is applied to the module. Correct functionality is
not ensured if either a reset deassertion or a change in the interface selection occurs when
the functional clock USBHS_FCLK is already running.
3222
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
