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High-Speed USB OTG Controller
22.1.5.3 Enabling MSTANDBY in Force-Standby Mode
The USBOTG.
[0] ENABLEFORCE bit controls MSTANDBY behavior in
force-standby mode only (see
). In this mode, only when the internal core is idle (the module
has no activity; that is, the USB is in suspend state) and when 1 is written to this bit, MSTANDBY goes
high. Similarly, when ENABLEFORCE is 0 and the internal core is also in a non-idle state, MSTANDBY is
deasserted. This bit does not influence MSTANDBY behavior in all other modes, such as no-standby and
smart-standby.
22.1.5.4 Power Management Basic Programming Model
This section describes the settings for optimal High-Speed USB controller power management, depending
on the use of this module in the application.
Two registers are involved in power management: USBOTG.
and
USBOTG.
On reset, the high-speed USB controller has the following configuration:
•
Master interface power management is in force-standby mode (USBOTG.
MIDLEMODE field = 0x0).
•
Slave interface power management is in force-idle mode (USBOTG.
[4:3]
SIDLEMODE field = 0x0).
•
Internal clock autogating feature is disabled (USBOTG.
[0] AUTOIDLE bit = 0).
•
MSTANDBY signal assertion is enabled (USBOTG.
[0] ENABLEFORCE bit = 1).
22.1.5.4.1 High-Speed USB Controller Not Used for Application
In this scenario, the high-speed USB controller is not used by the system software. Default settings must
be changed to reduce power consumption. Enabling the internal clock autogating feature cuts off the
module internal interface clock as soon as it is no longer required. This is done by setting the
USBOTG.
[0] AUTOIDLE bit to 1.
The optimal configuration when the high-speed USB controller is not used by the application is as follows:
•
Master interface power management is in force-standby mode (USBOTG.
MIDLEMODE field = 0x0).
•
Slave interface power management is in force-idle mode (USBOTG.
[4:3]
SIDLEMODE field = 0x0).
•
Internal clock autogating feature is enabled (USBOTG.
[0] AUTOIDLE bit = 1).
•
MSTANDBY signal assertion enabled (USBOTG.
[0] ENABLEFORCE bit = 1)
22.1.5.4.2 High-Speed USB Controller in Host Mode
When used as a host, the high-speed USB controller must be programmed as follows:
•
Master interface power management in smart-standby mode
•
Slave interface power management in smart-idle mode
•
Internal clock autogating feature enabled
•
MSTANDBY signal assertion disabled
The programming sequence must be as follows:
1. Write 0 to the USBOTG.
[0] ENABLEFORCE bit to disable the MSTANDBY
assertion before programming to smart-standby and smart-idle modes.
2. Set the USBOTG.
[13:12] MIDLEMODE field to 0x2, the
[4:3] SIDLEMODE field to 0x2, and the USBOTG.
[0]
AUTOIDLE bit to 0 to program the smart-standby and smart-idle modes. Ensure that internal clock
autogating is not enabled while programming smart-idle mode.
3. Set the USBOTG.
[0] AUTOIDLE bit to 1 to cut off the internal clocks to save power.
3227
SWPU177N – December 2009 – Revised November 2010
High-Speed USB Host Subsystem and High-Speed USB OTG Controller
Copyright © 2009–2010, Texas Instruments Incorporated
