Texas Instruments OMAP36 Series, Technical Reference Manual

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High-Speed USB OTG Controller
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Table 22-18. OTG_SIMENABLE
Address Offset 0x0000 0410
Physical Address Instance USBHS
See Table 22-9
Description Enable simulation acceleration features.
WARNING: For simulations only, since those features have an impact on USB protocol.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
TM1
Bits Field Name Description Type Reset
31:1 RESERVED reserved R 0x0000 0000
0 TM1 Test Mode 1 enabling (timer shortcuts) RW 0
Table 22-19. Register Call Summary for Register OTG_SIMENABLE
High-Speed USB OTG Controller
• Enable Simulation Acceleration Features : [0]
• High-Speed USB OTG Controller Registers : [1]
Table 22-20. OTG_FORCESTDBY
Address Offset 0x0000 0414
Physical Address Instance USBHS
See Table 22-9
Description Enabling MSTANDBY in FORCESTANDBY mode.
Type RW
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RESERVED
ENABLEFORCE
Bits Field Name Description Type Reset
31:1 RESERVED Reserved R 0x0000 0000
0 ENABLEFORCE Enabling MSTANDBY to go high RW 1
Table 22-21. Register Call Summary for Register OTG_FORCESTDBY
High-Speed USB OTG Controller
• Clocking, Reset, and Power-Management Scheme : [0] [1] [2] [3] [4] [5]
• Basic Operation : [6]
• Enabling MSTANDBY in Force-Standby Mode : [7]
• Power Management Basic Programming Model : [8] [9] [10] [11] [12] [13] [14]
• High-Speed USB OTG Controller Registers : [15]
3232 High-Speed USB Host Subsystem and High-Speed USB OTG Controller SWPU177N – December 2009 – Revised November 2010
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