Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Basic Programming Model
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5.4.4.6.1 Assigning a Logical Channel to a Trigger Event
The 64 DMA channels and the 8 QDMA channels can be flexibly mapped to any of the 128 available
PaRAM entries (see
Figure 5-13 ).
Any of the 64 DMA channels can be mapped to any of the 128 PaRAM entries through DMA
channel-mapping registers
TPCC_DCHMAPi (i = 0 to 63).
Any of the 8 QDMA channels can be mapped to any of the 128 PaRAM entries through QDMA
channel-mapping registers
TPCC_QCHMAPj (j = 0 to 7).
5.4.4.6.2 Manual Trigger (Software-Synchronized Transfers)
When a logical channel is defined and prioritized, the user can assign the logical channel (or the first in
the chained list) to a trigger event (from 0 to 63) by writing the number of the logical channel (PaRAMEntry
#) to one of the DMA channel-mapping registers
TPCC_DCHMAPi (i = 0 to 63). Then, the user can
manually start the transfer (one logical channel or a chained list of logical channels) by writing 1 to the bit
in the
TPCC_ESR or TPCC_ESRH register associated with the trigger event of the logical channel (or the
first logical channel in the chained list).
NOTE: The event does not need to be enabled in the TPCC_EER register to be manually triggered.
Example:
/* ---------------------------------------------- */
/*To manually start defined logical channel #0x3, uses event #20 */
/* ---------------------------------------------------- */
DCHMAP[20] = (DCHMAP[20] & ~(0x1FF<<5)) | 0x3<<5;
ESR = 1 << 20;
5.4.4.6.3 Hardware Trigger (Hardware-Synchronized Transfers)
When a logical channel is defined and prioritized, the user can assign the logical channel (or the first in
the chained list) to a trigger event (from 0 to 19) by writing the number of the logical channel (PaRAMEntry
#) to one of the DMA channel-mapping registers
TPCC_DCHMAPi (i = 0 to 19). The user can allow this
logical channel to be triggered by an associated hardware DMA request by writing 1 in the associated bit
of the EER register. The mapping of a hardware DMA request to DMA events is fixed. The mapping of
DMA requests to device peripheral sources is listed in
Table 5-2 .
Example:
/* ---------------------------------------------------- */
/* Associate defined logical channel #0x5 to UART3_DMA_TX*/
/* UART3_DMA_TX is DMA request #10 and associated to evt #10 */
/* ---------------------------------------------------- */
DCHMAP[10] = (DCHMAP[10] & ~(0x1FF<<5)) | 0x5<<5;
5.4.4.6.4 Automatic Trigger (QDMA)
The user can specify a trigger word from among any of the eight 32-bit words of the logical channel
context (PaRAM entry) for QDMA. Writing to the trigger word triggers the channel controller of QDMA to
issue a transfer request. The trigger word field of the QDMA channel mapping register
TPCC_QCHMAPj
(where j = {0 to 7}) defines the trigger word for a particular QDMA channel, as shown in Figure 5-13 .
This flexibility enables the CPU to selectively modify only the PaRAM entry that requires modification, and
thereby trigger the transfer. For example, after a transfer, if only count must change, QCHMAP can be
configured so that count is the trigger word, and a write to it automatically triggers the transfer.
Example:
/* ---------------------------------------------------- */
/* Associate defined logical channel #0x5 to QDMA #1 */
/* ---------------------------------------------------- */
762 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated