Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
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Bits Field Name Description Type Reset
9 E41 Event #41 R 0
8 E40 Event #40 R 0
7 E39 Event #39 R 0
6 E38 Event #38 R 0
5 E37 Event #37 R 0
4 E36 Event #36 R 0
3 E35 Event #35 R 0
2 E34 Event #34 R 0
1 E33 Event #33 R 0
0 E32 Event #32 R 0
Table 5-275. Register Call Summary for Register TPCC_CERH
IVA2.2 Subsystem Functional Description
• EDMA : [0]
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [1]
Table 5-276. TPCC_EER
Address Offset 0x1020
Physical address 0x01C0 1020 Instance IVA2.2 TPCC
Description Event Enable Register:
Enables DMA transfers for ER.En pending events. ER.En is set based on externally asserted events (through
tpcc_eventN_pi). This register has no effect on Chained Event Register (CER) or Event Set Register (ESR). Note
that if a bit is set in ER.En while EER.En is disabled, no action is taken. If EER.En is enabled at a later point (and
ER.En has not been cleared through SW) then the event will be recognized as a valid TR Sync EER.En is not
directly writeable. Events can be enabled through writes to EESR and can be disabled through writes to EECR
register.
EER.En = 0: ER.En is not enabled to trigger DMA transfers.
EER.En = 1: ER.En is enabled to trigger DMA transfers.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
E19 E18 E17 E16 E15 E14 E13 E12 E11 E10
Bits Field Name Description Type Reset
31:20 Reserved Reserved R 0
19 E19 Event #19 R 0
18 E18 Event #18 R 0
17 E17 Event #17 R 0
16 E16 Event #16 R 0
15 E15 Event #15 R 0
14 E14 Event #14 R 0
13 E13 Event #13 R 0
12 E12 Event #12 R 0
11 E11 Event #11 R 0
10 E10 Event #10 R 0
9 E9 Event #9 R 0
8 E8 Event #8 R 0
7 E7 Event #7 R 0
6 E6 Event #6 R 0
5 E5 Event #5 R 0
900 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
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