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IVA2.2 Subsystem Functional Description
A channel is a specific event that can cause a transfer to be submitted to the TPTCs as a transfer request.
The TPCC supports up to 64 DMA channels and up to 8 QDMA channels. These channels are identical,
except for the ways they are triggered:
•
DMA channels can be triggered by external events (such as McBSP TX Evt and McBSP RX Evt) by
the software writing 1 to a given bit location or channel, by the event set register, or through chaining.
•
QDMA channels are triggered automatically (auto-triggered) by the CPU using the IDMA. QDMAs
allow a minimum number of linear writes (optimized for the DSP IDMA feature) to be issued to the
TPCC to force a series of transfers to occur.
The TPCC arbitrates among all pending DMA/QDMA events with a fixed 64:1 and 4:1 priority encoder for
DMA and QDMA events, respectively (a low channel number corresponds to a high priority). DMA events
are always higher priority than QDMA events. The higher-priority event is placed in the event queue to
await submission to the transfer controller, which occurs at the earliest opportunity. Each event queue is
serviced in FIFO order, with a maximum of 16 queued events per event queue. If more than one TPTC is
ready to be programmed with a transmission request (TR), the event queues are serviced with fixed
priority, Q0 higher than Q1. When an event is ready to be queued and both the event queue and the TC
channel are empty, the event bypasses the event queue and goes directly to the PaRAM processing logic
for submission to the appropriate TC. If the TR bus/PaRAM processing is busy, the bypass path is not
used. The bypass is not used to dequeue for a higher-priority event.
Events are extracted from the event queue when the TPTC is available for a new TR to be programmed
into the TPTC (signaled with the empty signal, indicating an empty program register set). As an event is
extracted from the event queue, the associated PaRAM entry is processed and submitted to the TPTC as
a TR. The TPCC updates the appropriate counts and addresses in the PaRAM entry in anticipation of the
next trigger event for that PaRAM entry. The PaRAM entry consists of eight words of DMA context,
including source address, destination address, count, indexes, etc.
5.3.2.1.1.2 DMA Versus QDMA
The only difference between a QDMA and a DMA transfer is the specific means of generating/recognizing
TR synchronization. From the user point of view, DMA and QDMA transfer types can be combined to
perform various types of transfers.
DMA channel TR synchronization can be generated from one of three sources:
•
Event-triggered: The event register (
) channel n bit is set as the result of an external event.
An external event is latched in the event register. If the corresponding event is enabled through the
event enable register (
), this is recognized as a TR synchronization.
•
Manually triggered: The event set register channel n bit is set manually to the event set register
(
and
registers) for channel n (
[n] En bit or
[n] En
bit). Manually set events do not need to be enabled to be recognized as a TR synchronization.
•
Chain-triggered: The chain event register channel n (
and
registers) bit is set
when a chaining completion code is detected on the completion interface for channel n. Chain events
do not need to be enabled. If a chain trigger is detected, this is always recognized as a TR
synchronization.
QDMA TR synchronization occurs one of two ways:
•
Auto-triggered: The QDMA event register channel n (
and
H[n] En) bit is set
when a CPU write address matches the address defined by the QDMA mapping register for channel n
(
) and the QDMA channel is enabled (
[n] En bit field).
•
Link-triggered: The
[n] En bit is set when a link update is performed on a PaRAM address
that matches the
setting, and the
[n] En bit is set.
There is a subtle difference between each trigger type and the associated enablers. Event assertion
always results in the
[n] En bit being set, regardless of the state of the enable (
.En).
It is recognized as a TR synchronization only if enabled. Chain triggering always sets the
[n]
En bit and is always treated as a TR synchronization. Manual triggering always sets the
[n] En
bit and is always treated as a TR synchronization. Auto-triggering (QDMA) sets only the event register
[n] En bit only if the corresponding event is enabled (
[n] En); when the
[n] En bit is set, it is always treated as a TR synchronization.
For more information, see
, IVA2.2 Subsystem Basic Programming Model.
719
SWPU177N – December 2009 – Revised November 2010
IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated