Texas Instruments OMAP36 Series, Technical Reference Manual

Page: 893 / 3738

Public Version
www.ti.com
IVA2.2 Subsystem Register Manual
Table 5-262. TPCC_ER
Address Offset 0x1000
Physical address 0x01C0 1000 Instance IVA2.2 TPCC
Description Event Register:
If ER.En bit is set and the EER.En bit is also set, then the corresponding DMA channel is prioritized vs. other
pending DMA events for submission to the TC. ER.En bit is set when the input event #n transitions from inactive
(low) to active (high), regardless of the state of EER.En bit. ER.En bit is cleared when the corresponding event is
prioritized and serviced. If the ER.En bit is already set and a new inactive to active transition is detected on the
input event #n input AND the corresponding bit in the EER register is set, then the corresponding bit in the Event
Missed Register is set. Event N can be cleared through sw by writing 1 to the ECR pseudo-register.
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
E9 E8 E7 E6 E5 E4 E3 E2 E1 E0
E19 E18 E17 E16 E15 E14 E13 E12 E11 E10
Bits Field Name Description Type Reset
31:20 Reserved Reserved R 0
19 E19 Event #19 R 0
18 E18 Event #18 R 0
17 E17 Event #17 R 0
16 E16 Event #16 R 0
15 E15 Event #15 R 0
14 E14 Event #14 R 0
13 E13 Event #13 R 0
12 E12 Event #12 R 0
11 E11 Event #11 R 0
10 E10 Event #10 R 0
9 E9 Event #9 R 0
8 E8 Event #8 R 0
7 E7 Event #7 R 0
6 E6 Event #6 R 0
5 E5 Event #5 R 0
4 E4 Event #4 R 0
3 E3 Event #3 R 0
2 E2 Event #2 R 0
1 E1 Event #1 R 0
0 E0 Event #0 R 0
Table 5-263. Register Call Summary for Register TPCC_ER
IVA2.2 Subsystem Functional Description
• EDMA : [0] [1]
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [2]
893 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated