Texas Instruments OMAP36 Series, Technical Reference Manual, Page: 854 / 3738

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IVA2.2 Subsystem Register Manual
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Bits Field Name Description Type Reset
7:6 Reserved Write 0s for future compatibility. RW 0
Read returns 0.
5 SR 0: Supervisor Read access is not permitted RW 1
1: Supervisor Read access is permitted
4 SW 0: Supervisor Write access is not permitted RW 1
1: Supervisor Write access is permitted
3 Reserved Write 0s for future compatibility. Read returns 0. RW 0
2 UR 0: User Read access is not permitted RW 1
1: User Read access is permitted
1 UW 0: User Write access is not permitted RW 1
1: User Write access is permitted
0 Reserved Write 0s for future compatibility. Read returns 0. RW 0
Table 5-184. Register Call Summary for Register L1DMPPAk
IVA2.2 Subsystem Basic Programming Model
• Internal Memory : [0] [1] [2] [3] [4] [5]
IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [6]
5.5.5 TPCC Registers
This section provides information about the TPCC module. Each register in the module is described
separately below.
5.5.5.1 TPCC Register Mapping Summary
Table 5-185. TPCC Register Summary
Register Name Type Register Address Offset Physical Address
Width (Bits)
TPCC_PID R 32 0x0000 0x01C0 0000
TPCC_CCCFG R 32 0x0004 0x01C0 0004
TPCC_DCHMAPi
(1)
RW 32 (0x4*i) 0x01C0 0100 + (0x4*i)
TPCC_QCHMAPj
(2)
RW 32 (0x4*j) 0x01C0 0200 + (0x4*j)
TPCC_DMAQNUM0 RW 32 0x0240 0x01C0 0240
TPCC_DMAQNUM1 RW 32 0x0244 0x01C0 0244
TPCC_DMAQNUM2 RW 32 0x0248 0x01C0 0248
TPCC_DMAQNUM3 RW 32 0x024C 0x01C0 024C
TPCC_DMAQNUM4 RW 32 0x0250 0x01C0 0250
TPCC_DMAQNUM5 RW 32 0x0254 0x01C0 0254
TPCC_DMAQNUM6 RW 32 0x0258 0x01C0 0258
TPCC_DMAQNUM7 RW 32 0x025C 0x01C0 025C
TPCC_QDMAQNUM RW 32 0x0260 0x01C0 0260
TPCC_QUETCMAP RW 32 0x0280 0x01C0 0280
TPCC_QUEPRI RW 32 0x0284 0x01C0 0284
TPCC_EMR R 32 0x0300 0x01C0 0300
TPCC_EMRH R 32 0x0304 0x01C0 0304
TPCC_EMCR W 32 0x0308 0x01C0 0308
TPCC_EMCRH W 32 0x030C 0x01C0 030C
TPCC_QEMR R 32 0x0310 0x01C0 0310
TPCC_QEMCR W 32 0x0314 0x01C0 0314
(1)
i = 0 to 63
(2)
j = 0 to 7
854 IVA2.2 Subsystem SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated