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IVA2.2 Subsystem Basic Programming Model
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Table 5-21. Request-Type Access Controls
Bit Name
Description
SR
Supervisor can read
SW
Supervisor can write
SX
Supervisor can execute
(1)
UR
User can read
UW
User can write
UX
User can execute
(1)
(1)
IVA_XMC.L1DMPPAXX do not implement these bits.
For each bit, writing 1 permits the access type, and writing 0 denies it. For instance, setting the UX bit
to 1 means that user mode can execute from the given page. The DSP megamodule allows specifying
all six of these bits separately. For L1P, L1D, and L2 memories, and for EDMA, these bits are defined
in IVA_XMC.
[5:0], IVA_XMC.
[5:0], IVA_XMC.
[5:0], and
[5:0] and
[5:0], respectively.
NOTE:
IVA_XMC.
do not implement the SX and UX bit, because execution is not
possible from L1D memory. Therefore, these bits are reserved and should not be used in
these registers.
•
Other registers
The memory protection block records the address of the fault in the peripheral memory protection fault
address register (MPFAR). It records the rest of the information about the fault in the peripheral
memory protection fault status register (MPFSR); this register is formatted similarly to the MPPA.
Software can write to the memory protection fault command register (MPFCR).
The MPFAR corresponds to the following registers: IVA_XMC.
for L1P memory,
IVA_XMC.
for L1D memory, IVA_XMC.
for L2 memory, IVA_IDMA.
for IDMA, and
for EDMA.
The MPFSR corresponds to the following registers: IVA_XMC.
for L1P memory,
IVA_XMC.
for L1D memory, IVA_XMC.
for L2 memory, IVA_IDMA.
for IDMA, and
for EDMA.
Using the MPFSR register, a memory protection fault can be decoded as follows by software:
–
If the LOCAL status bit is set to 1, the request was a local DSP CPU request to its own memories.
Otherwise (if the LOCAL status bit is set to 0), the VBUS ID of the faulting requestor is in the
MPFSR[15:9] field.
–
The value of the access type field (SR, SW, SX, UR, UW, UX) indicates the type of access that was
at fault.
The MPFAR and MPFSR store information for only one fault. The hardware block holds the fault
information until the software clears it by writing to MPFCR.
The user clears the recorded fault by setting the MPFCR[0] MPFCLR bit to 1. Writing 1 to this bit
clears both MPFAR and MPFSR registers. The MPFAR and MPFSR read-only registers do not
respond to writes. Once the user clears the fault, the hardware records the next protection violation,
and signals an exception when it occurs. Writing 1 to any other bit of the MPFCR has no effect on the
memory protection registers. Writing 0 to the MPFCR[0] MPFCLR bit also has no effect.
The MPFCR corresponds to the following registers: IVA_XMC.
for L1P memory,
IVA_XMC.
for L1D memory, IVA_XMC.
for L2 memory, IVA_IDMA.
for IDMA, and
for EDMA.
•
Events generated to DSP megamodule IC block
Internal events are generated to inform the DSP megamodule module for memory protection:
–
CCMPINT (EVT28) is generated for a TPCC memory protection interrupt.
–
SYS_CMPA (EVT 119) is generated in case of a SYS CPU memory protection fault.
–
PMC_CMPA (EVT120) and PMC_DMPA (EVT121) are generated in case of CPU and DMA
memory protection faults, respectively, on PMC.
–
DMC_CMPA (EVT122) and DMC_DMPA (EVT123) are generated in case of CPU and DMA
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IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
