Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
5 SR 0: Supervisor Read access is not permitted RW 1
1: Supervisor Read access is permitted
4 SW 0: Supervisor Write access is not permitted RW 1
1: Supervisor Write access is permitted
3 SX 0: Supervisor eXecute access is not permitted RW 1
1: Supervisor eXecute access is permitted
2 UR 0: User Read access is not permitted RW 1
1: User Read access is permitted
1 UW 0: User Write access is not permitted RW 1
1: User Write access is permitted
0 UX 0: User eXecute access is not permitted RW 1
1: User eXecute access is permitted
Table 5-168. Register Call Summary for Register L2MPPAj
IVA2.2 Subsystem Basic Programming Model
• Internal Memory : [0] [1] [2] [3] [4]
• Powering Down L2$ Memory While IVA2 is Active : [5] [6] [7]
IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [8]
Table 5-169. L1PMPFAR
Address Offset 0x0000 A400
Physical address 0x0184 A400 Instance IVA2.2 GEMXMC
Description PMC
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR
Bits Field Name Description Type Reset
31:0 ADDR Fault Address R 0x00000000
Table 5-170. Register Call Summary for Register L1PMPFAR
IVA2.2 Subsystem Basic Programming Model
• Internal Memory : [0]
IVA2.2 Subsystem Register Manual
• XMC Register Mapping Summary : [1]
Table 5-171. L1PMPFSR
Address Offset 0x0000 A404
Physical address 0x0184 A404 Instance IVA2.2 GEMXMC
Description PMC
Type R
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved FLTID ATYP
Reserved
849 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
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