L1PMPPA 31
L1PMPPA 15
L1PMPPA 16
L1PMPPA 0
0x00E0 0000 – 0x00E0 07FF
0x00E0 7800 – 0x00E0 7FFF
Unmapped memory,
reserved registers
Region 1
32KB (flat/cache RAM)
Page size = 2KB
Region 0
iva2-042
Public Version
IVA2.2 Subsystem Basic Programming Model
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5.4.9 Memory Management
5.4.9.1
External Memory
5.4.9.1.1 Cacheability
The L1P, L1D, and L2 cache sizes are all 0K byte after reset.
•
The user enables the L2 cache by writing 0x2 (maximum cache is 64K bytes) to the IVA_XMC.
register.
•
However, this is not sufficient, because the region external to the IVA2.2 is configured as a noncached
area after reset. The user must configure the external area to be cached by setting the
IVA_XMC.
[0] PC bit to 1, i referring to the index of the related 16-MB page (starting from i = 16
for the first external page at address 0x1000 0000).
The MAR settings only control the L2 and L1D cache's response to CPU data and program fetches. L1P
caches the memory range regardless of the values of the MAR bits.
5.4.9.1.2 Virtual Addressing
The device embeds two instances of MMU: one instance is camera MMU (also named MMU1) dedicated
to the camera subsystem; the other instance is IVA2.2 MMU (also named MMU2) used by the IVA2.2
subsystem. For more information about MMU2 software settings at IVA2.2 boot, see
,
Example of IVA2.2 Boot.
For a complete programming guide of IVA2.2 MMU, see
, Memory Management Units.
5.4.9.2
Internal Memory
5.4.9.2.1 Memory Protection
The DSP megacell memory protection divides the memory map into pages and defines a per-page
permission structure. This permission structure is in the MPPA registers: IVA_XMC.
,
, IVA_XMC.
for L1P, L1D, L2 memory protection, and
for EDMA memory protection.
, and
show which
register corresponds to each page permission structure.
Figure 5-31. L1P Memory Protection Registers
788
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
