Restore MMU context
from external memory
Restore DMA context
from external memory
Enable interrupt
in the INTC
Wake-up event on IVA2
IVA2 ready
Configure L1D, L1P, and L2 cache/flat memory
iva2-047
Public Version
IVA2.2 Subsystem Basic Programming Model
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Figure 5-36. IVA2 Wake Up
5.4.10.4 Powering Down L2$ Memory While IVA2 is Active
If the L2$ is unused while the DSP is active, the IVA2.2 can completely switch off the 96-KB SRAM
attached to the L2$ controller. This typically happens when the DSP is running at a low frequency (for
instance, at the same frequency as the SDRAM) where L2$ is not justified. The alternative is to switch off
L2$ SRAM completely, losing all L2-cache content and memory-mapped SRAM (from 0x10800000 to
0x1080FFFF). It is impossible to put the SRAM in low-leakage mode and retain data/program while the
DSP is active. Also, L2 cache SRAM is the only memory/cache that supports this off mode while DSP is
active. L1D and L1P cache SRAM off modes are not supported while DSP is active.
The sequence to enter L2$ off mode while DSP is active follows:
1. Save
and disable the L2$ by converting L2-cache SRAM to memory-mapped SRAM only
(96KB):
.L2MODE = 0x0.
2. Read back
to ensure that Step 1 is complete.
3. Save
(j = 0 to 31) and write 0x0 to the
(j = 0 to 31) registers to report access to L2
memory (for debug) and enable associated permission check interrupt and/or exception.
4. Configure the PRCM to switch off L2:
PRCM.PM_PWSTCTRL_IVA2.SHAREDL2CACHEFLATONSTATE = 0x0.
5. Read back PRCM.PM_PWSTCTRL_IVA2 to ensure that Step 4 is complete.
After this sequence, the user must not access the L2 memory. If this happens (typically in code under
debug), a memory-protection interrupt and/or exception is taken.
The sequence to exit L2$ off mode (while DSP is active) follows:
800
IVA2.2 Subsystem
SWPU177N – December 2009 – Revised November 2010
Copyright © 2009–2010, Texas Instruments Incorporated
