Texas Instruments OMAP36 Series, Technical Reference Manual

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IVA2.2 Subsystem Register Manual
Bits Field Name Description Type Reset
31:13 Reserved Read returns 0. R 0x00000
12:9 FID Faulted ID: R 0x0
FID register contains valid info if any of the MP error bits (UXE,
UWE, URE, SXE, SWE, SRE) are non-zero (i.e., if an error has been
detected.) The FID field contains the VBus PrivID for the specific
request/requestor that resulted in a MP Error.
8:6 Reserved Read returns 0. R x0
5 SRE Supervisor Read Error: R 0
SRE = 0: No error detected.
SRE = 1: Supervisor level task attempted to Read from a MP Page
without SR permissions.
4 SWE Supervisor Write Error: R 0
SWE = 0: No error detected.
SWE = 1: Supervisor level task attempted to Write to a MP Page
without SW permissions.
3 SXE Supervisor Execute Error: R 0
SXE = 0: No error detected.
SXE = 1: Supervisor level task attempted to Execute from a MP
Page without SX permissions.
2 URE User Read Error: R 0
URE = 0: No error detected.
URE = 1: User level task attempted to Read from a MP Page without
UR permissions.
1 UWE User Write Error: R 0
UWE = 0: No error detected.
UWE = 1: User level task attempted to Write to a MP Page without
UW permissions.
0 UXE User Execute Error: R 0
UXE = 0: No error detected.
UXE = 1: User level task attempted to Execute from a MP Page
without UX permissions.
Table 5-255. Register Call Summary for Register TPCC_MPFSR
IVA2.2 Subsystem Basic Programming Model
• Internal Memory : [0]
IVA2.2 Subsystem Register Manual
• TPCC Register Mapping Summary : [1]
Table 5-256. TPCC_MPFCR
Address Offset 0x0808
Physical address 0x01C0 0808 Instance IVA2.2 TPCC
Description Memory Protection Fault Command Register
Type W
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved
MPFCLR
Bits Field Name Description Type Reset
31:1 Reserved Write 0s for future compatibility. W 0x00000000
0 MPFCLR Fault Clear register: W 0
CPU write of 1 to the MPFCLR bit causes any error conditions
stored in MPFAR and MPFSR registers to be cleared.
CPU write of 0 has no effect.
889 SWPU177N – December 2009 – Revised November 2010 IVA2.2 Subsystem
Copyright © 2009–2010, Texas Instruments Incorporated